3D IC Interconnection via Sacrificial Element Removal
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Solution Overview
Problem
High-temperature heat treatment in the production of 3D integrated circuits can degrade conductor materials used for inter-level connections, leading to inefficiencies and reliability issues.
Innovation Solution
A method involving the formation of sacrificial elements through a porous layer, followed by their removal using an etching agent, allows for the preservation of conductor material by deferring the formation of inter-level connection elements and avoiding excessive thermal exposure, using materials like copper or tungsten, and potentially replacing the porous layer with a dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature heat treatment is applied to activate dopants in 3D integrated circuits, then transistor activation is improved, but conductor material degrades
Solution Approach 1:
The patent applies preliminary action by forming the conductor material for inter-level connections before the high-temperature heat treatment step. Specifically, conductor plugs are formed in through-holes through the porous layer before the heat treatment that activates dopants in the transistor. This sequencing allows the conductor material to be placed early while avoiding its exposure to degrading high temperatures, thus resolving the contradiction between achieving transistor activation and preserving conductor material integrity.
2Productivity
If conductor material is formed early for inter-level connections, then connection elements are available, but conductor material degrades during subsequent heat treatment
Solution Approach 1:
The patent uses a porous layer as an intermediary structure that enables early formation of conductor plugs while protecting them from subsequent heat treatment. The porous layer allows the conductor material to be deposited in through-holes before the heat treatment step, and its porous structure facilitates later removal or replacement. This intermediary approach allows productivity to be maintained through early connection element formation while reliability is preserved by isolating the conductor material from degrading thermal exposure.
3Ease of manufacture
If sacrificial elements are removed before support formation, then element removal is easier and thermal exposure is reduced, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the manufacturing process into distinct sequential stages: first forming sacrificial elements in the porous layer, then removing them before support formation, and finally forming the support structure. This segmentation of the process allows each step to be optimized independently - the sacrificial element removal can be performed when access is easiest, before the support structure is in place, while the support formation follows as a separate, simplified step. The segmentation resolves the contradiction by making the removal process easier while managing overall process complexity through clear stage separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of 3D integrated circuits with preserved conductor materials, maintaining their integrity and functionality while avoiding the degradation caused by high-temperature processes, thus enhancing the reliability and efficiency of inter-level connections.
Implementation Method 1
removing the sacrificial element(s) of the first openings, using an etching agent of the sacrificial material, the etching agent being capable of being introduced through the porous layer(s)
Data Source
AI summary
Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.