3D IC Interlayer Metal Structure for Shorter Vertical Connections

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Solution Overview

Problem

Existing integrated circuit (IC) devices face challenges in reducing the size and improving performance by optimizing electrical connections between stacked semiconductor devices, which often result in increased resistance and capacitance, and require complex manufacturing processes.

Innovation Solution

Implementing a multilayer structure with interlayer metal structures that electrically couple top and bottom semiconductor devices, reducing the length and resistance/capacitance of connections and simplifying manufacturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If semiconductor devices are stacked in layers to reduce IC device size, then area efficiency is improved, but resistance and capacitance of electrical connections increase

Engineering Contradiction:
ImproveIC device areaVSAvoidelectrical connection quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from planar 2D connections to 3D vertical connections by implementing interlayer metal structures that extend through multiple semiconductor layers. This dimensional change allows electrical connections to be made directly between stacked devices, reducing connection length and improving electrical performance while maintaining compact area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces interlayer metal structures as intermediary elements between stacked semiconductor devices. These metal structures serve as conductive pathways that facilitate electrical coupling between layers, acting as mediators that resolve the connection quality degradation inherent in direct stacked configurations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If complex manufacturing processes are used to improve electrical connections between stacked devices, then connection quality is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connection qualityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple manufacturing operations into integrated process steps. The interlayer metal structures are formed using consolidated deposition and patterning steps that simultaneously create multiple connection points, reducing the total number of discrete manufacturing operations while maintaining connection quality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interlayer metal structures serve multiple functions: they provide electrical coupling between devices, act as interconnect pathways, and enable vertical integration. This multi-functionality reduces the need for separate specialized structures, thereby simplifying the overall manufacturing process.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If connection length between stacked devices is reduced, then resistance and capacitance decrease, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connection qualityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements preliminary alignment features and pre-formed interlayer metal structures that establish connection pathways before final device assembly. This preliminary action ensures that alignment tolerances are built into the structure design, reducing the precision demands on subsequent manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250357435A1Integrated circuit device and method
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250357435A1 patent drawing
  • US20250357435A1 patent drawing
  • US20250357435A1 patent drawing

AI summary

An integrated circuit (IC) device includes a bottom semiconductor device, a top semiconductor device over the bottom semiconductor device in a thickness direction of the IC device, and a multilayer structure between the bottom semiconductor device and the top semiconductor device in the thickness direction. The multilayer structure includes a lower dielectric layer over the bottom semiconductor device, an upper dielectric layer over the lower dielectric layer, and an interlayer metal structure between the lower dielectric layer and the upper dielectric layer.