3D IC I/O Multiplexing for Compact, X-Free Chip Testing
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Solution Overview
Problem
In designing 3D ICs, the vertical stacking of chips can lead to increased chip size and design complexity if the characteristics of the I/O circuits are not considered.
Innovation Solution
The integrated circuit includes a multiplexing circuit to select I/O targets based on selection signals, a test enable circuit to manage test operations, and a test control circuit to facilitate testing, with through silicon vias for electrical connections, minimizing area and preventing signal propagation issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple I/O circuits are provided for each chip in 3D IC, then testing capability is improved, but chip area and design complexity increase
Solution Approach 1:
The multiplexing circuit enables a single I/O circuit to serve multiple functions by dynamically selecting between different I/O targets (IP cores or chip connection circuits) based on operation mode. This multi-functionality eliminates the need for separate dedicated I/O circuits for testing, thereby reducing chip area while maintaining comprehensive testing capability.
Solution Approach 2:
The system dynamically reconfigures the I/O circuit connections through the multiplexing circuit, allowing the same physical I/O circuit to be dynamically assigned to different targets depending on whether the system is in normal operation mode or test mode. This dynamic allocation optimizes resource utilization and reduces the total number of I/O circuits required.
2Reliability
If separate I/O circuits are dedicated for testing in 3D IC, then testing accuracy is improved, but design complexity increases
Solution Approach 1:
The multiplexing circuit provides a universal interface that handles both normal operation and testing functions through a single I/O circuit structure. This unified approach simplifies the overall design by eliminating the need for separate dedicated test I/O circuits, thereby reducing design complexity while maintaining testing accuracy through proper signal routing control.
Solution Approach 2:
The multiplexing circuit acts as an intermediary between the I/O circuit and multiple targets (IP cores and chip connection circuits). This mediator selectively connects the I/O circuit to the appropriate target based on the operation mode, providing a simplified design interface that manages complexity internally while presenting a uniform interface to the outside world.
3Ease of manufacture
If X-propagation is allowed in through silicon vias, then signal transmission is simplified, but testing accuracy deteriorates
Solution Approach 1:
The test enable circuit proactively prevents X-propagation in through silicon vias before it can affect testing accuracy. By detecting when testing is in progress and actively blocking unwanted signal propagation through the vias, the system eliminates the harmful effect of X-propagation that would otherwise compromise test measurements, while allowing normal signal transmission during operational modes.
Solution Approach 2:
The system dynamically controls the behavior of through silicon vias through the test enable circuit, switching between allowing signal transmission during normal operation and blocking X-propagation during testing. This dynamic control mechanism adapts the via behavior to the current operational context, maintaining both ease of manufacture and testing accuracy.
Data Source
AI summary
An integrated circuit and a test system including the same are provided. Provided is an integrated circuit including a plurality of first semiconductor intellectual property (IP) cores, a chip connection circuit including a first through silicon via, a second through silicon via, a receiver electrically connected to the first through silicon via, and a driver electrically connected to the second through silicon via, a multiplexing circuit configured to select an input/output (I/O) target selection signal, a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit, and a test control circuit configured to provide the I/O target selection signal to the multiplexing circuit.