3D IC Transistor Layer Transfer via Ion-Cut
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Solution Overview
Problem
Current methods for constructing Three Dimensional Integrated Circuits (3D ICs) face challenges such as limited TSV density due to misalignment issues, high defect density in silicon processed by selective epitaxy, and difficulties in maintaining high-performance transistors with low-temperature processing, which restricts the scalability and reliability of 3D ICs.
Innovation Solution
The development of a 3D IC system with a first semiconductor layer of interconnected transistors and a second mono-crystallized semiconductor layer, where the second layer is transferred from a reusable donor wafer using low-temperature ion-cut techniques, enabling high-density interconnects and horizontal transistor orientation, and allowing for the construction of high-performance transistors without the need for high-temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Thru Silicon Vias (TSV) are used to connect bonded wafers in 3D ICs, then electrical connections between layers are achieved, but the density of TSVs is limited due to large landing pads required for alignment and the large diameter of TSVs
Solution Approach 1:
The patent transitions from planar TSV connections to vertical FinFET transistor structures, utilizing the third dimension (vertical channel) to achieve higher density interconnections. The FinFET architecture allows for increased interconnection density by exploiting vertical space rather than relying on large lateral landing pads.
Solution Approach 2:
The patent changes the fundamental parameters of the interconnection approach by moving from bulk silicon TSVs to nanoscale FinFET structures with controlled channel width and height. This parameter change enables much smaller feature sizes and higher density connections.
2Ease of manufacture
If selective epitaxy is used to process silicon for stacked transistors, then transistor layers are formed, but the silicon has high defect density which reduces performance and stability
Solution Approach 1:
The patent replaces thermal/chemical epitaxial growth processes with a mechanical layer transfer approach using ion-cut technology. This substitution eliminates the defect formation mechanisms inherent in selective epitaxy while maintaining the ability to form stacked transistor structures.
Solution Approach 2:
The patent discards the defective silicon substrate after layer transfer and recovers only the thin active device layer. This approach eliminates the bulk defects present in epitaxially grown silicon while preserving the functional transistor structures.
3Reliability
If high-temperature processing is used to create high-performance transistors with mono-crystalline silicon channels, then transistor performance is improved, but the underlying metallization and low-k intermetal dielectric cannot withstand such temperatures
Solution Approach 1:
The patent performs preliminary formation of the active device layers and their metallization on a separate donor wafer before transferring to the final substrate. This allows the sensitive metallization to be processed at appropriate temperatures independently, while the transistor performance is optimized through the high-quality mono-crystalline structure transferred via ion-cut.
Solution Approach 2:
The patent segments the fabrication process into independent stages: forming active layers on a donor wafer, transferring them via ion-cut, and then completing device formation on the final substrate. This segmentation allows different processing conditions to be applied to different components without mutual interference.
4Reliability
If low-temperature processing is used to maintain reliability of underlying metallization, then metallization reliability is preserved, but it is difficult to achieve high-performance transistors without mono-crystalline silicon channels
Solution Approach 1:
The patent introduces an intermediary donor wafer that serves as a temporary platform for forming high-quality mono-crystalline transistor structures. These structures are then transferred to the final substrate, acting as a mediator that enables high-performance transistors to be created without subjecting the underlying metallization to high temperatures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density, low-power, and high-performance 3D ICs with improved connectivity, reduced fabrication costs, and extended battery life, while allowing for the integration of diverse components and enhanced design flexibility.
Implementation Method 1
the second layer is transferred from a reusable donor wafer using low-temperature ion-cut techniques
Data Source
AI summary
A device, including: an integrated circuit chip, where the integrated circuit chip includes: a first layer including a plurality of first transistors including a mono-crystal channel; at least one metal layer overlying the first layer, the at least one metal layer including aluminum or copper and providing interconnection between the first transistors; a second layer overlying the at least one metal layer, the second layer including second horizontally oriented transistors including a second mono-crystal channel; and a through the second layer via of diameter less than 150 nm, where the second horizontally oriented transistors are interconnected to form logic circuits.