3D IC Transistor Stacking via Layer Transfer and Ion-Cut Alignment
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Solution Overview
Problem
Current 3D IC fabrication methods face challenges in achieving high transistor performance and density due to limitations in Through-Silicon Via (TSV) density, alignment issues, and the need for high-temperature processing, which affects the reliability and efficiency of interconnects and transistor performance.
Innovation Solution
The method involves layer transfer techniques using preprocessed CMOS wafers with low-temperature bonding and ion-cut processes to align and couple transistors with high precision, enabling the formation of high-density interconnects and maintaining transistor performance without excessive heat exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through-Silicon Via (TSV) method is used for 3D IC fabrication, then interconnect density is improved, but manufacturing precision deteriorates due to alignment issues and large landing pad requirements
Solution Approach 1:
The patent transitions from planar 2D IC fabrication to three-dimensional 3D IC stacking, adding the vertical dimension (z-axis) to the traditional horizontal (x-y plane) interconnect architecture. This enables interlayer vias to connect multiple active layers vertically, dramatically increasing interconnect density without requiring proportionally larger landing pads, as the vias exploit the third dimension for routing.
Solution Approach 2:
The patent divides the monolithic IC structure into multiple discrete active layers that are bonded together. Each layer can be processed and thinned independently, with TSVs formed through selectively thinned regions. This segmentation allows precise control over via formation and reduces alignment complexity by processing layers separately before bonding.
2Quantity of substance
If wafer thinning is performed to enable TSV fabrication, then interconnect density is improved, but reliability deteriorates due to handling difficulties and yield loss
Solution Approach 1:
The patent performs wafer thinning and TSV formation as preliminary actions on individual layers before the bonding step. By preparing the layers in advance with thinned regions and pre-formed vias, the fragile thinned wafers do not require extensive post-bonding handling, reducing the risk of damage and yield loss during subsequent processing steps.
Solution Approach 2:
The patent introduces carrier substrates or handle wafers as intermediaries to support and protect the thinned active layers during handling and processing. These intermediary substrates provide mechanical strength to the fragile thinned wafers, enabling safe manipulation and assembly without direct handling of the delicate thinned regions.
3Reliability
If high-temperature processing is used for transistor fabrication, then transistor performance is improved, but device complexity increases due to metallization reliability constraints
Solution Approach 1:
The patent segments the fabrication process into high-temperature steps performed on individual active layers before bonding, and lower-temperature steps performed after bonding. This allows each layer to be processed at optimal high temperatures for transistor formation without exposing the complete stacked structure to temperatures that would damage the interlayer metallization and dielectrics.
Solution Approach 2:
The patent performs high-temperature transistor fabrication as a preliminary action on the active layers before they are bonded together. By completing all high-temperature processing steps while the layers are still separate and supported by their original substrates, the patent avoids the need to protect sensitive post-bonding interconnect structures from thermal damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of 3D IC devices with improved transistor alignment, increased interconnect density, and reduced power consumption, enhancing performance and density while maintaining reliability and efficiency.
Implementation Method 1
ion-cut processes to align and couple transistors with high precision
Implementation Method 2
low-temperature bonding
Data Source
AI summary
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.