Transistor TRIZ Cases

A Fin-FET fabrication method extracts dummy gates to form metal gates within precise trenches.

Polygonal contact electrodes fill through-holes between bridge and sensor portions, reducing contact resistance while maintaining structural integrity.

V-shaped substrate recesses filled with stressed silicon germanium improve energy efficiency while managing manufacturing precision constraints.

Laser annealing a reducing metal layer on an oxide semiconductor creates conductive source and drain contact zones.

Dummy transistors adjust offset voltage via drain capacitance, reducing process variations without increasing circuit area.

Segmented terminal groups average reference voltages across mixed signal line regions, reducing dividing line visibility despite low transistor mobility.

Varying passivation thickness in the peripheral area resolves the trade-off between robustness against external charges and moisture-related corrosion.

A graphene carbon layer resolves lattice mismatch issues by enabling high-quality thin film growth and transfer to flexible substrates.

A stacked layer structure with a planarization stop layer exposes top surfaces in cell array and peripheral circuits regions simultaneously.

Layered silicon oxide and nitride films block material intrusion between adjacent word lines, preventing parasitic capacitance increase and electrical leakage.

Deep trenched floating gates in the termination area block leakage paths, maintaining high breakdown voltage despite shallow prior art structures.

A memory latch circuit uses oxide semiconductor transistors to minimize leakage current paths between power supply and ground potentials.

A stacked oxide semiconductor transistor structure reduces off-state current to enable long-term data retention without refresh operations.

Titanium nitride templates enable selective deposition of ruthenium or copper to resolve conductivity limitations in thin integrated circuitry.

A charging stop circuit disconnects the bootstrap capacitor from the high voltage potential during dead times to prevent wasteful current flow.

A doped field cut region applies tensile stress to boost carrier mobility without increasing parasitic capacitance between adjacent transistors.

Dynamic back-gate control adjusts SRAM transistor threshold voltage, resolving the trade-off between cell stability and area scaling.

Multi-layer insulating pattern with metal-based dielectric supports orthogonal bit lines, reducing necking and bending.

A deformation preventing layer offsets thermal stress on a substrate surface to maintain flatness during high temperature processing.

Sidewall composition controls threshold voltage in high-k gate insulating films, reducing dispersion from impurity fluctuations.

Silicide layers formed via thermal annealing lower contact resistance while a dielectric layer prevents electrical breakdown and leakage current.

Oxide-to-oxide bonding joins single crystal transistor layers while through-silicon vias enable high-density interconnects without damaging lower wiring.

A back-illuminated imaging sensor uses a specific doping profile to reduce dark current noise.

A semiconductor device uses a threshold-modulating film to trap charge and adjust the read transistor voltage.

A semiconductor link region connects intrinsic and extrinsic base layers in a bipolar junction transistor structure.

A dual liner silicide fabrication method for CMOS devices uses protective layers and self-aligned dielectric deposition to form source and drain liners.

Ion-cut layer transfer aligns stacked transistors to resolve TSV density and alignment trade-offs while maintaining reliability.

Segmented pixel groups with dedicated detection signal lines enable simultaneous radiation amount reading.

A vertical CMOS inverter structure positions a high-k dielectric layer directly on a boron-doped silicon germanium source/drain region to enable controlled programming.

Segmented gate structure controls core and edge threshold voltages independently, resolving STI corner parasitic effects that lower device stability.

A semiconductor device design uses vertical and horizontal channel orientations to produce distinct gate lengths for core and input/output transistors.

Alternating silicon oxynitride layers with matched refractive indices enhance light transmittance in thin film transistor substrates.

Vertical transient voltage suppressor uses asymmetric doping regions to achieve symmetric breakdown voltages.

A dual-gate thin-film transistor uses unequal gate capacitance to amplify photoelectric signals within an image sensor array.

Surrounding the fin with a gate electrode utilizes the entire channel surface, increasing operating current and suppressing short channel effects.

A floating electrode electrically connected to the data line decreases resistance without increasing thickness, preventing substrate warping and stains.

Elongated vias connect parallel conductive members in semiconductor capacitor plates, resolving lithography alignment issues and leakage currents.

A semiconductor stressor region forms bi-layer dislocations through sequential pre-amorphous implantation and annealing to enhance carrier mobility.

Nanosheet stacks with distinct doping profiles create gate-all-around transistors on a single substrate.

A power device integrates a Schottky diode with the drift region to enable faster switching speeds.

A 10T dual-port SRAM cell design segments metal routing across multiple layers to simplify interconnects.

Series diodes adjust trigger voltage in electrostatic protection circuits, resolving leakage current trade-offs during normal operation.

Offset conductive meshes form contacts at intersections to resolve lithography limits on packing density while maintaining electrical connection efficiency.

Alternating n-type and p-type strips in transistor extension regions create lateral electric fields that enhance depletion.

A display device integrates a light-shielding conductive layer directly with the first electrode to block stray light.

Conformal cap layer protects gate stack side surfaces, reducing channel length variation and dielectric damage in flash memory cells.

Connecting a dummy floating gate electrode to a word line equalizes potentials, preventing non-uniform movable ion distribution in interlayer insulating films.

White emission layer paired with capping layers of varying refractive indices and thicknesses to optimize light extraction across subpixels.