MOSFET Core-Edge Threshold Voltage Segmentation
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Solution Overview
Problem
In semiconductor processing, parasitic effects in the STI corner regions of MOSFETs cause threshold voltage lowering and homogenous device property assumptions are difficult to model, especially for devices with small body region widths, leading to process margin issues in sensitive circuit elements.
Innovation Solution
A semiconductor structure with a body region comprising a core and edge region, where the edge region is surrounded by a dielectric region and controlled by a gate structure providing different threshold voltages for the core and edge regions, allowing for homogenous switching characteristics by adjusting the gate structure's doping and thickness to reduce the influence of edge regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If shallow trench isolation (STI) is used to electrically isolate adjacent FETs, then device integration is achieved, but parasitic effects in STI corner regions cause threshold voltage lowering and modeling difficulties
Solution Approach 1:
The body region is segmented into a core region and edge regions, with the gate structure divided into a first gate region overlapping the core region and a second gate region overlapping the edge regions. This segmentation allows independent control of threshold voltages in different areas, enabling the core region to have a first threshold voltage and the edge regions to have a second threshold voltage, thereby resolving the parasitic threshold voltage lowering issue while maintaining device integration
Solution Approach 2:
Different regions of the gate structure are doped with different doping types or concentrations: the first gate region overlapping the core region has a first doping type/concentration, while the second gate region overlapping the edge regions has a second doping type/concentration. This local quality differentiation compensates for parasitic effects in edge regions and improves threshold voltage stability without compromising integration
2Area of moving object
If the body region width is reduced to increase device density, then integration density improves, but homogenous device property assumptions become difficult to model
Solution Approach 1:
By segmenting the gate structure into a first gate region and a second gate region that overlap with the core region and edge regions respectively, the patent enables independent threshold voltage control. This allows accurate modeling of device properties even in small width devices where edge effects are significant, thereby maintaining manufacturing precision while increasing device density
Solution Approach 2:
The patent changes the doping parameters (type and concentration) of different gate regions to compensate for edge effects. The first gate region has doping parameters optimized for the core region, while the second gate region has doping parameters specifically tuned to counteract parasitic effects in edge regions, enabling accurate modeling and homogeneous device properties at small dimensions
Data Source
AI summary
According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.