SRAM Interconnect Sidewall Spacer Fin Formation
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Solution Overview
Problem
The existing methods for forming sub-lithographic fin thickness in FinFET SRAM devices require additional masks, increasing manufacturing costs and introducing overlay errors, which are undesirable for high-density SRAM applications.
Innovation Solution
A method involving the formation of a sidewall spacer around a patterned poly-silicon layer on a semiconductor substrate, using a cap layer and spacer materials like nitride, oxide, or oxynitride, to reduce the need for additional masks and improve lithographic process windows, thereby forming an improved SRAM interconnect structure with reduced contact and metal wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an additional mask is used to cut the spacer image to achieve desired circuit layout, then sub-lithographic fin thickness is achieved, but manufacturing cost increases and overlay errors are introduced
Solution Approach 1:
The spacer structure performs dual functions: it defines the sub-lithographic fin thickness and simultaneously serves as the interconnect structure. The spacer is formed by depositing conformal layers around a mandrel, and after mandrel removal, the spacer automatically defines both the fin dimensions and the interconnect path, eliminating the need for separate patterning masks.
Solution Approach 2:
The spacer structure is designed to perform multiple functions within a single component: it acts as both the dimensional template for sub-lithographic fin formation and as the functional interconnect wiring. This multi-functionality consolidates what would traditionally require separate masking and patterning steps into a unified process.
2Manufacturing precision
If an additional mask is used to cut the spacer image, then desired circuit layout is achieved, but manufacturing cost increases due to higher material and tool consumption
Solution Approach 1:
The spacer structure defines its own pattern through conformal deposition geometry rather than requiring external mask definition. The mandrel dimensions and spacer thickness control the final interconnect dimensions, using the deposition process itself to define the pattern rather than requiring separate photolithography masking steps.
Solution Approach 2:
The invention extracts the patterning function from the traditional mask-based photolithography process and embeds it within the conformal deposition and mandrel removal process. The pattern is defined by the geometry of the deposited layers and mandrel, not by external masks, thereby eliminating mask-related costs.
3Manufacturing precision
If an additional mask is used for multiple patterning, then sub-lithographic dimensions are achieved, but new processes are required increasing complexity
Solution Approach 1:
The spacer formation process inherently provides the sub-lithographic patterning through conformal deposition physics. The mandrel dimensions combined with controlled spacer thickness automatically define sub-lithographic features without requiring additional patterning masks or complex multi-step lithography processes.
Solution Approach 2:
The invention uses parameter control in the deposition process (spacer thickness, mandrel dimensions, deposition conformality) to achieve sub-lithographic dimensions. By precisely controlling these physical parameters rather than relying on additional lithographic patterning steps, sub-lithographic features are obtained through physical deposition control rather than multiple patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of SRAM interconnects with reduced contact and metal congestion, enhancing SRAM stability and reducing manufacturing costs by eliminating the need for additional masks and improving lithographic process windows.
Implementation Method 1
depositing a cap layer on the silicon layer; depositing a poly-silicon layer on the cap layer
Implementation Method 2
depositing a cap layer on the silicon layer; depositing a poly-silicon layer on the cap layer
Implementation Method 3
etching the portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer for forming a gate oxide
Data Source
AI summary
A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the portion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.