Semiconductor Memory Stacked Gate Structure
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Solution Overview
Problem
Current semiconductor memory devices fail to meet the demands for high operating speed, high storage density, and low bit cost, making them unsuitable for individual intended purposes despite the increasing need for higher capacity and reduced costs in data handling.
Innovation Solution
A semiconductor memory design featuring a stacked gate structure with oxide semiconductor layers, insulating layers, and distinct gate electrodes for transistors, allowing for efficient charge storage and control through a combination of word lines, bit lines, and injection lines, enabling quick data write and read operations without high voltage tunneling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor memory structures are used, then manufacturing processes are simpler, but operating speed and storage density cannot meet high-capacity demands
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked structures, where memory cells are arranged vertically across multiple layers. This dimensional change enables significantly higher storage density by utilizing the vertical space above the substrate, allowing multiple bit lines and word lines to intersect at different heights and form multiple memory cells per lateral footprint area.
Solution Approach 2:
The patent implements nested structures where conductive layers, insulating layers, and semiconductor layers are stacked within each other vertically. Each layer is embedded within the structure formed by previous layers, creating a compact nested arrangement that maximizes storage capacity within a limited volume while maintaining electrical connectivity through vertical channels.
2Speed
If high voltage tunneling effects are used for write operations, then write speed improves, but transistor degradation increases
Solution Approach 1:
The patent replaces high-voltage electrical tunneling mechanisms with low-voltage field effect transistor switching mechanisms. Instead of relying on quantum tunneling through thick oxide layers that causes degradation, the invention uses controlled electric fields to modulate channel conductivity in thin-film transistors, enabling write operations at lower voltages that do not degrade the transistor structure.
Solution Approach 2:
The patent changes the operating voltage parameters from high voltage (required for tunneling) to low voltage (sufficient for field effect switching). By adjusting the gate voltage of the thin-film transistors, the patent achieves effective write operations without the harmful high electric fields that cause transistor degradation, thus improving reliability while maintaining operational speed.
3Quantity of substance
If memory capacity is increased to meet data handling demands, then storage density improves, but bit cost reduction becomes more difficult
Solution Approach 1:
The patent merges multiple functional layers (conductive layers, insulating layers, semiconductor layers) into a single integrated three-dimensional structure. By combining storage elements, address lines, and control circuits into a unified stacked architecture, the patent increases memory capacity while utilizing shared resources across layers, thereby reducing the cost per bit through improved manufacturing efficiency and reduced material usage.
Data Source
AI summary
According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.