Semiconductor Pillar Width Variation for Threshold Voltage Control
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Solution Overview
Problem
Pillar-shaped insulated gate field effect transistors (pillar-FETs) face challenges in achieving desired threshold voltages due to reduced impurity concentration dependence, leading to issues like reduced source-to-drain punch-through breakdown voltage and PN junction breakdown voltage, especially when pillar width decreases.
Innovation Solution
The semiconductor device incorporates first and second semiconductor pillars with different widths, allowing for a greater change in threshold voltage by adjusting pillar width, enabling the same channel impurity concentration to produce transistors with varying threshold properties without excessive impurity concentration changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pillar width is decreased to improve the on-current to off-current ratio, then the threshold voltage control capability deteriorates due to reduced impurity concentration dependence
Solution Approach 1:
The patent applies local quality by creating different pillar widths in different regions of the semiconductor device. Specifically, first pillar-shaped insulated gate field effect transistors have a first pillar width while second pillar-shaped insulated gate field effect transistors have a second pillar width that is larger than the first. This allows each region to have optimized characteristics: thinner pillars for higher on/off ratio and thicker pillars for better threshold voltage control through impurity concentration adjustments.
Solution Approach 2:
The patent utilizes parameter changes by varying the pillar width dimension to achieve different transistor characteristics. By changing the pillar width parameter, the device can optimize the balance between on-current to off-current ratio and threshold voltage control. The patent specifically sets the second pillar width to be larger than the first pillar width to compensate for reduced impurity concentration dependence in thinner pillars.
2Ease of operation
If excessively high or low impurity concentration is used to achieve desired threshold voltage when impurity concentration dependence is reduced, then the source-to-drain punch-through breakdown voltage and PN junction breakdown voltage deteriorate
Solution Approach 1:
The patent applies local quality by assigning different pillar width specifications to different transistor types: first pillar-shaped insulated gate field effect transistors use a first pillar width optimized for high on/off ratio, while second pillar-shaped insulated gate field effect transistors use a second pillar width (larger than the first) optimized for threshold voltage control. This regional differentiation eliminates the need for extreme impurity concentrations in any single region.
Solution Approach 2:
The patent segments the semiconductor device into multiple regions with different pillar width characteristics. By dividing the device into first and second pillar-shaped insulated gate field effect transistors with different pillar widths, the patent creates specialized zones that can operate within safe impurity concentration ranges while achieving their respective performance targets.
Data Source
AI summary
Disclosed is a semiconductor device comprising a semiconductor substrate including first, second and third surfaces, the second surface being placed above the first surface, the third surface having first and second edges connecting to the first and second surfaces, respectively; an isolation region including an insulator and formed on the first and third surfaces; an active region including the second surface and fenced with the insulator of the isolation region; and first and second semiconductor pillars each protruding upwardly from the second surface in the active region, wherein the first semiconductor pillar is thinner than the second semiconductor pillar.