Semiconductor Gate Stack TiN Thickness Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively controlling and managing the threshold voltages of transistors, particularly in achieving distinct threshold voltages for different types of transistors within a single device, which is crucial for optimizing performance and efficiency in logic and memory applications.
Innovation Solution
The semiconductor device incorporates multiple gate stacks with varying thicknesses of TiN layers and high-k layers, along with specific metal and barrier layers, to control the threshold voltages of n-channel and p-channel transistors, ensuring distinct voltage thresholds for each type of transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple gate stacks with different TiN layer thicknesses are used to control threshold voltages of different transistors, then threshold voltage control precision is improved, but device structure complexity increases
Solution Approach 1:
The gate stack is segmented into multiple functional layers including high-k dielectric layer, TiN layer, and metal gate layer. Each layer serves a specific function in threshold voltage control, allowing independent optimization of each segment's thickness and material properties to achieve precise threshold voltage control for different transistors while maintaining a modular structure
Solution Approach 2:
Different TiN layer thicknesses are applied locally to different gate stacks based on the specific threshold voltage requirements of each transistor type (e.g., thicker TiN for NFET, thinner TiN for PFET). This localized variation in layer thickness enables precise threshold voltage control for each transistor while using a统一的 multi-layer gate stack architecture
2Adaptability or versatility
If high-k dielectric layers with greater thickness are used to achieve desired threshold voltages, then threshold voltage range is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the TiN layer thickness as a primary mechanism to adjust threshold voltage. By varying the TiN thickness from approximately 5nm to 15nm across different gate stacks, the patent achieves a threshold voltage range of approximately 0.3V to 0.7V, providing adaptability for different transistor types without requiring extreme variations in high-k layer thickness
Solution Approach 2:
The gate stack employs a composite structure combining high-k dielectric material (such as HfO2) with TiN and metal gate layers. This composite material approach allows the high-k layer to provide the necessary dielectric strength and threshold voltage modulation capability, while the TiN and metal gate layers provide work function control, distributing the precision requirements across multiple material components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of threshold voltages, enhancing the performance and efficiency of both logic and memory transistors by optimizing their operating conditions based on their respective voltage requirements.
Implementation Method 1
a first TiN layer which is formed on the first high-k layer to contact the first high-k layer and has a first thickness
Implementation Method 2
a first high-dielectric constant (k) layer which is formed on the substrate
Data Source
AI summary
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.