3D Semiconductor Device Planarization via Concave Region and Stop Layer
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Solution Overview
Problem
The challenge in manufacturing three-dimensional semiconductor devices is the high cost and limited scalability of existing two-dimensional semiconductor devices, which restricts the integration level and mass production due to the need for expensive processing equipment and complex fine pattern forming technologies.
Innovation Solution
A method involving the formation of a concave region in a substrate with a stacked layer structure that includes a planarization stop layer, allowing for the simultaneous exposure of top surfaces in the cell array and peripheral circuits regions, enabling efficient planarization and reducing processing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used to increase integration, then fine pattern forming technology must be advanced, but expensive processing equipment is required which limits mass production
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. By stacking multiple memory cell layers vertically, the device achieves higher integration density without requiring finer lateral patterning, thus avoiding the need for expensive advanced lithography equipment while maintaining manufacturing feasibility.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing memory cells, word lines, and bit lines. This segmentation allows each layer to be formed using standard processing techniques, and the layers are subsequently stacked to achieve high integration without requiring single-step fine patterning of the entire high-density structure.
2Productivity
If three-dimensional semiconductor memory devices are proposed to increase integration, then vertical stacking is achieved, but new process technologies are required for mass production
Solution Approach 1:
The patent forms a sacrificial layer structure before forming the final memory stack. This preliminary sacrificial structure serves as a template that guides the formation of the vertical memory channels and enables subsequent selective removal to create the desired three-dimensional structure, simplifying the overall manufacturing process.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary element during manufacturing. This sacrificial layer is temporarily formed to enable precise positioning and formation of the vertical memory structure, then selectively removed to complete the device. This intermediary approach simplifies the direct formation of complex three-dimensional structures.
3Productivity
If stacked layer structure is formed conformally to increase vertical integration, then different top surfaces are created in cell array and peripheral circuits regions, but complex planarization is required
Solution Approach 1:
The patent applies different treatments to different regions: the cell array region receives the full stacked layer structure for high-density storage, while the peripheral circuits region has selective removal of layers to accommodate circuit requirements. This local differentiation allows each region to have the appropriate structure for its function without requiring complex planarization across the entire wafer.
Solution Approach 2:
The patent selectively removes portions of the stacked layer structure in the peripheral circuits region by controlling the etch depth to expose specific layers only where needed. This extraction approach creates the necessary structural differences between cell array and peripheral regions without requiring extensive planarization processes.
Data Source
AI summary
According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.