Vertical Gate Fabrication via Inverted Process Sequence
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with vertical gates face challenges in preventing void formation due to narrow spaces between active pillars, which complicates the etch-back process and can lead to the removal of word lines in affected regions.
Innovation Solution
A method involving the formation of a stack structure with pillar regions having a wider upper portion and a narrower lower portion, where a conductive layer is positioned between a dielectric layer and a hard mask layer, allowing for selective etching to create vertical gates that serve as both gate electrodes and word lines, preventing void formation by forming the conductive layer before active pillars are formed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conventional method deposits the second conductive layer to form word lines after forming active pillars, then the word lines can be formed, but large voids are formed due to the narrow space between active pillars
Solution Approach 1:
The conductive layer is deposited and patterned to form vertical gates before the active pillars are formed. This preliminary action prevents void formation because the conductive layer is deposited on a planar substrate rather than in the narrow spaces between already-formed pillars. The etch-back process then forms the final vertical gate structure without encountering voiding issues.
Solution Approach 2:
The conventional sequence is inverted: instead of forming active pillars first and then depositing conductive material, the conductive layer is deposited and patterned first to create vertical gates, and then active pillars are formed around them. This inversion eliminates the narrow space problem that causes void formation during deposition.
2Reliability
If the etch-back process is performed on the second conductive layer to form word lines, then word lines are formed, but all word lines may be altogether removed in severely-affected regions due to voids
Solution Approach 1:
The conductive layer is deposited and etched back to form vertical gates before active pillars are formed. This preliminary formation of the conductive structure on a planar surface ensures uniform etch-back results and prevents the complete removal of word lines that occurs when voids are present during the etch-back process.
3Productivity
If the active pillars are formed with narrow spacing to increase integration density, then integration level improves, but voids form during subsequent conductive layer deposition
Solution Approach 1:
The conductive layer is deposited and patterned to form vertical gates before the active pillars are formed. This allows high integration density to be achieved with narrow pillar spacing without compromising conductive layer deposition quality, since the conductive material is deposited on a planar substrate rather than in narrow inter-pillar spaces.
Solution Approach 2:
The process transitions from a two-dimensional planar architecture to a three-dimensional vertical architecture. By forming vertical gates that extend in the vertical dimension before pillar formation, the method enables high integration density while avoiding the void formation problem that plagues conventional planar approaches with narrow spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents voids during conductive layer deposition, enabling stable formation of vertical gates in memory devices under 30 nm dimensions and improving the interface between gate electrodes and word lines, resulting in superior semiconductor device performance.
Implementation Method 1
The active pillars may be formed through an epitaxial growth process, and may include an epitaxial silicon layer formed through a selective epitaxial growth (SEG) process.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a stack structure including pillar regions whose upper portion has a wider width than a lower portion over a substrate, the lower portion including at least a conductive layer; forming a gate insulation layer on sidewalls of the pillar regions; forming active pillars to gap-fill the pillar regions; and forming vertical gates that serve as both gate electrode and word lines by selectively etching the conductive layer.