Selective Silicon Germanium Carbon Epitaxy for CMOS Integration
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Solution Overview
Problem
Conventional methods for epitaxial deposition of silicon germanium carbon layers in CMOS integrated circuits face challenges in protecting one type of transistor while performing epitaxy on the other, leading to device performance degradation and integration difficulties due to the need for additional spacers.
Innovation Solution
The process involves forming silicon germanium regions adjacent gate electrodes, using a hard mask to protect p-type regions while selectively removing silicon germanium from n-type regions, and then epitaxially growing silicon germanium carbon in place of the removed silicon germanium, eliminating the need for additional spacers and simplifying integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods use additional spacers to protect one transistor type during epitaxy, then selectivity is improved, but device performance degrades and integration becomes difficult
Solution Approach 1:
The patent extracts and removes the problematic additional spacers from the conventional process. By using a single hard mask layer that is selectively removed through etching, the method eliminates the need for multiple spacer structures, thereby reducing device complexity while maintaining manufacturing precision through selective epitaxial growth on the exposed surfaces.
Solution Approach 2:
The hard mask serves multiple functions: it protects the first transistor type during epitaxy, defines the pattern for selective removal, and enables subsequent processing steps. This multi-functional approach replaces the multiple specialized components (additional spacers) required in conventional methods, simplifying integration while maintaining selectivity.
2Reliability
If additional spacers are used for protection during epitaxy, then transistor protection is improved, but device performance degrades
Solution Approach 1:
The hard mask is designed as a temporary, disposable protective layer that is removed after serving its purpose. This single-use approach avoids the performance degradation caused by permanent or multi-step spacer structures, maintaining device performance while providing necessary protection during the epitaxial process.
3Manufacturing precision
If conventional patterning methods are used with additional spacers, then selectivity is improved, but defect rates increase
Solution Approach 1:
The patent merges the protection function and patterning function into a single hard mask layer, eliminating the need for separate spacer formation and multiple patterning steps. This consolidation reduces the number of process steps and interfaces where defects can occur, thereby maintaining selectivity while reducing defect rates in the resulting circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration of silicon germanium carbon layers, reducing device performance degradation and defect rates by allowing selective epitaxial growth under hard mask remnants, thereby improving the fabrication process for CMOS integrated circuits.
Implementation Method 1
Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium
Data Source
AI summary
Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.