Flash Memory Silicide Contact Resistance Reduction
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Solution Overview
Problem
The self-aligned contact process used in forming conducting structures on source and drain regions in flash memory devices leads to poor performance, stability, and reliability due to potential electrical breakdown and leakage current.
Innovation Solution
A flash memory fabrication method involving the formation of silicide layers on source and drain regions through a thermal annealing process, followed by the creation of a metal layer on the source trench bottom and sidewalls, which serves as a source wire, and the formation of conducting structures in a dielectric layer with a predetermined distance to prevent electrical breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conducting structures are formed on source and drain regions through self-aligned contact process, then manufacturing precision is improved, but reliability deteriorates due to electrical breakdown and leakage current
Solution Approach 1:
The conducting structure formation is divided into two separate processes: first forming silicide layers on source and drain regions, then forming conducting structures in dielectric layer. This segmentation prevents direct contact between conducting structures and source/drain regions, eliminating electrical breakdown while maintaining alignment precision through the self-aligned nature of the silicide formation.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the conducting structures and the source/drain regions. This dielectric layer prevents direct electrical contact that causes breakdown and leakage current, while still allowing the conducting structures to be positioned with high precision through the self-aligned silicide formation process.
2Productivity
If feature size of flash units is shrunk to reduce cost, then productivity is improved, but reliability deteriorates due to increased electrical breakdown risk
Solution Approach 1:
By separating the silicide layer formation from the conducting structure formation, the patent enables smaller feature sizes to be manufactured with higher precision through self-alignment, while the dielectric intermediary prevents electrical breakdown even at reduced dimensions, thus maintaining reliability while improving productivity.
Solution Approach 2:
The silicide layers are formed in advance on the source and drain regions before the conducting structures are created. This preliminary action establishes precise alignment references that enable subsequent conducting structure formation at smaller feature sizes without sacrificing reliability, as the self-aligned process maintains precision even when dimensions are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, enhances the reliability and stability of flash memory devices by preventing electrical breakdown and leakage current, while also simplifying the fabrication process.
Implementation Method 1
performing a thermal annealing process on the metal film to diffuse metal ions of the metal film into the substrate to form a first silicide layer on the source regions and a second silicide layer on the drain regions
Data Source
AI summary
A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance.