Back-Gated SRAM Cell Stability via Dynamic Threshold Control
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Solution Overview
Problem
As memory designs scale down to 45 nanometer design rule node dimensions, SRAM cell stability is compromised due to increased transistor leakage and parameter variation, leading to larger device sizes and higher costs, as previous approaches require longer channel lengths to maintain stability, resulting in increased system size and cost.
Innovation Solution
The implementation of back-gated and double-gated FinFETs in SRAM cells, where the back gate control line dynamically adjusts the threshold voltage during read and write operations to achieve balanced stability and reduced area requirements, using separate front and back gates or a single coupled gate structure to manage current drive ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFET transistors with channel lengths longer than the design rule node dimension are used to maintain SRAM cell stability, then SRAM cell stability is improved, but SRAM cell area increases
Solution Approach 1:
The patent applies back-gate voltage to dynamically adjust the threshold voltage of the MOSFET transistors. By changing the electrical parameter (threshold voltage) through back-gate control, the invention compensates for transistor variability and maintains SRAM cell stability without requiring longer channel lengths, thus avoiding area increase.
Solution Approach 2:
The invention introduces dynamic control of transistor characteristics through back-gate voltage adjustment during read and write operations. This dynamic parameter modulation allows the SRAM cell to adapt its threshold voltage in real-time, maintaining stability under varying operating conditions without fixed structural changes that would increase area.
2Loss of energy
If lower supply voltages are used to limit static power dissipation, then power consumption is reduced, but SRAM cell stability decreases due to increased transistor variability impact
Solution Approach 1:
The patent compensates for the reduced stability caused by low supply voltage through back-gate voltage control. By dynamically adjusting the threshold voltage via back-gate biasing, the invention offsets the impact of transistor variability that is exacerbated at lower supply voltages, maintaining adequate noise margins and read/write stability.
Solution Approach 2:
The back-gate control mechanism provides a feedback path to adjust transistor threshold voltages in response to operating conditions. This feedback control allows the SRAM cell to maintain stability by compensating for parameter variations that occur at low supply voltages, effectively decoupling power consumption from stability requirements.
3Manufacturing precision
If MOSFET transistors with longer channel lengths are used to reduce transistor variability impact, then threshold voltage variation is reduced, but device die size increases
Solution Approach 1:
Instead of relying on longer channel lengths to reduce threshold voltage variation, the patent uses back-gate voltage control to actively adjust and equalize threshold voltages across transistors. This electrical compensation method achieves threshold voltage consistency without the geometric constraint of longer channels, thereby preventing die size increase.
Solution Approach 2:
The back-gate voltage serves as an intermediary control mechanism that mediates between transistor variability and threshold voltage consistency. By introducing this intermediate control parameter, the invention achieves precise threshold voltage management without modifying the physical dimensions of the transistor channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances SRAM cell stability and reduces area requirements by dynamically controlling threshold voltage and current drive ratios, effectively addressing the challenges of scaling while maintaining accurate read and write operations without increasing device size.
Implementation Method 1
applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation
Data Source
AI summary
One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation.