Split Gate Device Recessed Region Drive Current
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Solution Overview
Problem
Split gate devices in nonvolatile memory arrays face reduced drive current due to the length of select and control gates, degrading reading performance.
Innovation Solution
A method for forming a split gate device with a rounded-corner recessed region adjacent the select gate, where portions of the charge storage layer and control gate are formed, allowing for improved isolation and increased drive current through thicker oxides and slanted interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the select gate and control gate are made longer to improve isolation and reduce bitcell disturb, then isolation performance is improved, but drive current is reduced which degrades reading performance
Solution Approach 1:
The gate structure is segmented into two separate gates (select gate and control gate) positioned at different locations. The select gate is positioned over the channel region while the control gate is positioned over the charge storage layer, allowing each gate to perform its specific function independently. This segmentation enables improved isolation through the separate select gate while maintaining adequate drive current through the optimized control gate positioning and the rounded-corner recessed region design.
Solution Approach 2:
The invention transitions from a conventional planar gate structure to a three-dimensional structure with rounded-corner recessed regions. The control gate extends into the recessed region formed by etching the substrate, creating a vertical dimension component. This dimensional change allows the control gate to be positioned closer to the charge storage layer while maintaining proper electrical isolation, thereby improving drive current without sacrificing isolation performance.
2Ease of manufacture
If conventional planar gate structures are used, then manufacturing is simpler, but drive current is reduced and reading performance is degraded
Solution Approach 1:
The invention introduces rounded corners at the intersections of the recessed regions and substrate surfaces, replacing sharp angular transitions with curved surfaces. This curvature is achieved through controlled etching processes that naturally form rounded corners. The rounded-corner design improves drive current by enhancing the electric field distribution and facilitating better charge storage layer formation, while still being compatible with standard semiconductor manufacturing processes.
Solution Approach 2:
The invention modifies the geometric parameters of the gate structure by creating recessed regions with specific depth and width dimensions. The rounded-corner recessed region has controlled dimensions that optimize the electric field distribution and charge storage layer formation. These parameter changes (depth, width, curvature radius) are tuned to maximize drive current while maintaining manufacturability through established etching and deposition processes.
3Power
If the substrate is recessed to form rounded-corner regions, then drive current and breakdown voltage are improved, but manufacturing complexity increases
Solution Approach 1:
The rounded-corner recessed regions are formed as preliminary structures before depositing the charge storage layer and control gate. The etching process that creates the recessed regions with rounded corners is performed first, establishing the geometric foundation for subsequent layer formation. This preliminary action simplifies the overall manufacturing process by pre-defining the optimal geometry for charge storage and electric field distribution, rather than requiring complex post-processing steps.
Data Source
AI summary
A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semiconductor layer adjacent to the first sidewall of the select gate. The thin layer of charge storage material is formed in which a first portion of the thin layer of charge storage material is formed in the first recess and a second portion of the thin layer of charge storage material is formed along the first sidewall of the first select gate. The control gate is formed over the first portion of the thin layer of charge storage material. The result is a semiconductor device useful a memory cell.