Semiconductor Gate Electrode Structure for Coupling Capacitance Reduction
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Solution Overview
Problem
The increasing integration in semiconductor devices leads to higher coupling capacitance between memory cell transistors due to narrower gaps between word lines, and the use of high dielectric constant insulating films, which is exacerbated by the introduction of wet treatments like DHF, causing etch back and voids in silicon oxide films, resulting in parasitic capacitance and electrical leakage.
Innovation Solution
The semiconductor device employs cobalt silicide formation after gate electrode formation, with a method that includes forming gate electrodes, filling silicon oxide films, alloying metal layers to form silicide, and depositing silicon nitride films in a configuration that prevents silicon nitride intrusion between gate electrodes, thereby reducing coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If silicon nitride film is formed on sidewalls of word line to reduce coupling capacitance, then coupling capacitance between adjacent memory cell transistors increases due to higher dielectric constant, but device characteristics deteriorate
Solution Approach 1:
The patent applies different dielectric materials with different dielectric constants to different regions: low dielectric constant material (silicon oxide) in the inter-word line region and high dielectric constant material (silicon nitride) on the sidewalls of the gate electrode. This local differentiation allows the sidewall region to provide charge control while the inter-word line region maintains low coupling capacitance.
Solution Approach 2:
The patent introduces an interlayer insulating film as an intermediary barrier between the silicon nitride film on the sidewall and the adjacent gate electrodes. This intermediary layer prevents direct capacitive coupling between adjacent word lines while allowing the silicon nitride film to fulfill its charge control function on the gate electrode sidewall.
2Reliability
If wet treatment such as DHF is introduced to clean polycrystalline silicon film surface for silicide reaction, then silicide reaction is ensured, but interlayer insulating film is etched back and voids are formed
Solution Approach 1:
The patent performs preliminary cleaning of the polycrystalline silicon film surface using a dry cleaning method or mild treatment before silicide formation, removing organic contaminants and natural oxide layers without introducing aggressive wet chemicals that would etch the interlayer insulating film. This preliminary action ensures sufficient surface cleanliness for silicide reaction while preserving the integrity of the overlying silicon oxide film.
Solution Approach 2:
The patent replaces the chemical wet cleaning process (DHF treatment) with a physical or mild chemical cleaning method such as oxygen plasma treatment or UV ozone treatment. These methods effectively clean the polycrystalline silicon surface by removing organic contaminants through oxidation and volatilization without causing etching of the silicon oxide interlayer insulating film.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents the increase in inter-electrode coupling capacitance and electrical leakage by physically blocking silicon nitride intrusion, ensuring stable device characteristics and performance.
Implementation Method 1
Thermal processing is subsequently performed to cause the aforementioned silicide alloying reaction
Implementation Method 2
a silicon nitride film, for example, effective in preventing intrusion of Cu is disposed as a barrier film between the gate electrodes and metal interconnects in order to prevent intrusion of Cu into the active regions
Implementation Method 3
interlayer insulating films are filled between the word lines
Data Source
AI summary
A semiconductor device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the gate insulating film, a second gate electrode formed on the gate insulating film between the first gate electrode and a contact plug, a first silicon oxide film formed above the substrate between the first and second gate electrodes, a first silicon nitride film formed along the substrate and a side surface of the second gate electrode between the contact plug and the second gate electrode, a second silicon oxide film formed on the first silicon oxide film, the first gate electrode and the second gate electrode, the second silicon oxide film including an upper surface having a height greater than the height of a first upper surface of the first gate electrode relative to the substrate, and a second silicon nitride film formed on the second silicon oxide film.