3D Stacked Transistors via Oxide Bonding and TSV Alignment
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Solution Overview
Problem
Current 3D stacked semiconductor chips face challenges in achieving high-density connections between layers due to misalignment issues and the need for high-temperature processing, which damages lower wiring layers and limits connectivity.
Innovation Solution
The method involves forming single crystal transistors and memory cells using lithographic and etch steps with alignment marks, allowing for oxide-to-oxide bonding and layer transfer techniques to create horizontally-oriented transistors with high-density connections, enabling sub-400°C processing temperatures without degrading existing layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (>700°C) is used to construct transistor layers, then transistor performance is improved, but lower wiring layers are damaged
Solution Approach 1:
The patent divides the 3D stacked structure into separate modules: bottom transistor layer, bottom wiring layer, top transistor layer, and top wiring layer. Each layer is constructed independently and then bonded together, allowing different processing temperatures for different layers. The bottom wiring layer is constructed at low temperature first, then the top transistor layer is constructed at high temperature on a separate substrate, and finally the two are bonded together using through-silicon vias to connect them.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical stacking. By arranging transistor layers and wiring layers in three dimensions with alternating stacking, the patent enables independent processing of different layers at appropriate temperatures. The vertical separation in the third dimension allows the bottom wiring layer to be protected from high-temperature damage while the top transistor layer achieves high performance through high-temperature processing.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay is reduced, but connectivity between layers is limited due to alignment issues and large contact sizes
Solution Approach 1:
The patent performs preliminary construction of the bottom layer (transistors and wiring) on one silicon wafer, and separately constructs the top layer (transistors and wiring) on another silicon wafer. Through-silicon vias are pre-formed in both layers before bonding. The wafers are then bonded together with precise alignment, and the pre-formed vias are connected to establish high-density inter-layer connectivity. This preliminary preparation enables accurate alignment and high connectivity density.
3Quantity of substance
If contact size is reduced to increase connection density, then connectivity between layers is improved, but alignment tolerance decreases and manufacturing difficulty increases
Solution Approach 1:
Through-silicon vias are pre-formed in both the bottom and top silicon wafers before bonding. These vias extend through the entire thickness of each wafer, creating robust connection pathways. The preliminary formation of these vias with appropriate dimensions and positioning enables high connection density while maintaining sufficient alignment tolerance during the bonding process, as the vias provide a larger target area for alignment compared to smaller contacts.
Data Source
AI summary
A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.