Trigate Device Fully Alloyed Source Drain
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Solution Overview
Problem
In FinFETs, the high conductivity epitaxial raised source/drain regions can cause electrical shorts between neighboring transistors and deep trench capacitors due to the merging of semiconductor fins and conductive strap structures during selective epitaxy, leading to increased on-resistance and reduced on-current.
Innovation Solution
The formation of fully alloyed source/drain regions through ion implantation and subsequent annealing, which reduces on-resistance and increases on-current by eliminating the need for selective epitaxy, thereby preventing electrical shorts between transistors and deep trench capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If epitaxial raised source/drain regions are formed, then on-current is increased, but unwanted shorts occur between adjacent semiconductor fin and conductive strap structure
Solution Approach 1:
The patent converts the potential harm of material growth into a benefit by using ion implantation to create dopant-rich regions that are then silicided. Instead of allowing uncontrolled epitaxial growth that causes shorts, the invention uses controlled ion implantation followed by silicidation to create fully alloyed source/drain regions that provide both high on-current and electrical isolation, turning the growth issue into a controlled doping and alloying process.
2Reliability
If selective epitaxy is performed to reduce on-resistance, then conductivity is improved, but manufacturing precision is compromised due to merging of neighboring structures
Solution Approach 1:
The patent replaces the mechanical/chemical growth process of selective epitaxy with an ion implantation and silicidation process. Instead of relying on controlled epitaxial growth that is sensitive to lateral merging, the invention uses direct ion implantation into defined regions followed by silicidation to create fully alloyed source/drain regions. This substitution of the fabrication mechanism eliminates the manufacturing precision issues associated with epitaxial growth while maintaining conductivity improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fully alloyed source/drain regions effectively reduce on-resistance, enhance on-current, and improve junction performance by segregating dopants at interfaces, thus preventing unwanted shorts and increasing the overall performance of FinFETs.
Implementation Method 1
source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation
Implementation Method 2
a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions
Implementation Method 3
The entire source/drain regions are alloyed with the metal
Implementation Method 4
a post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region
Data Source
AI summary
After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.