Semiconductor Device Gate Length Differentiation via Channel Orientation
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Solution Overview
Problem
In logic devices, core and input/output transistors require different gate lengths, which is challenging to achieve with existing finFET structures without additional patterning processes and masks.
Innovation Solution
A semiconductor device design where transistors with different impurity types and channel orientations (horizontal or vertical) are used, allowing for varying gate lengths based on voltage requirements, with specific impurity-doped semiconductor patterns and gate structures to accommodate both core and input/output transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional patterning processes using additional masks are used to implement different gate lengths in core and input/output transistors, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The transistor structure is segmented into distinct regions with different channel orientations. Core transistors use vertical channels while input/output transistors use horizontal channels, allowing different gate lengths to be achieved through structural segmentation rather than additional patterning steps. This segmentation enables simultaneous formation of different gate lengths in a single patterning process.
Solution Approach 2:
The invention transitions from varying gate lengths through additional planar patterning to achieving different gate lengths through three-dimensional structural orientation. By using vertical channels for core transistors and horizontal channels for input/output transistors, the gate length differentiation is achieved in the vertical dimension rather than through additional horizontal patterning steps, thereby reducing process complexity.
2Manufacturing precision
If finFET structure is used with additional patterning processes to achieve different gate lengths, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The finFET structure is designed to serve multiple functions simultaneously. The same basic finFET fabrication process is used for both core and input/output transistors, but the channel orientation (vertical vs. horizontal) provides different gate lengths. This multi-functionality allows a single patterning process to achieve what previously required multiple specialized patterning steps, improving ease of manufacture while maintaining precision.
Solution Approach 2:
Instead of achieving gate length differentiation through additional two-dimensional patterning steps, the invention uses three-dimensional channel orientation (vertical vs. horizontal) to achieve the same goal. This dimensional approach simplifies the fabrication process by eliminating the need for additional masks and patterning steps, thereby improving ease of manufacture while maintaining precise gate length control.
3Adaptability or versatility
If different gate lengths are implemented through additional patterning processes, then adaptability is improved, but productivity deteriorates
Solution Approach 1:
The transistor array is segmented into core transistor regions with vertical channels and input/output transistor regions with horizontal channels. This segmentation allows different transistor characteristics to be achieved through the structural design rather than through additional processing steps, thereby maintaining high manufacturing throughput while achieving the required adaptability for different transistor types.
Solution Approach 2:
The invention achieves transistor characteristic differentiation by utilizing channel orientation in three-dimensional space (vertical vs. horizontal) rather than through additional planar patterning steps. This approach maintains manufacturing productivity by avoiding extra processing steps while still providing the adaptability needed for different transistor types and gate lengths.
Data Source
AI summary
A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.