Stacked Semiconductor Layers with Offset Electrodes
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in increasing component density across semiconductor dies due to the complexity of stacking different types of components, such as n-on-p or p-on-n structures, which can lead to thermal budget issues and manufacturing inefficiencies.
Innovation Solution
The proposed solution involves a semiconductor device with stacked layers of the same type of components, such as nanosheet or fin layers, where overlapping and laterally offset configurations reduce thermal damage and simplify interconnections, allowing for efficient stacking of N-type or P-type transistors with overlapping gate regions and isolated source/drain electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If different types of components (n-on-p or p-on-n structures) are stacked to increase component density, then component density is improved, but thermal budget issues and manufacturing complexity increase
Solution Approach 1:
The patent applies homogeneity by stacking transistor layers of the same type (either all n-type or all p-type) rather than alternating between different types. This uniform stacking approach simplifies the manufacturing process while still achieving increased component density through vertical integration, directly resolving the contradiction between density improvement and manufacturing complexity
2Quantity of substance
If different types of components (n-on-p or p-on-n structures) are stacked to increase component density, then component density is improved, but thermal budget issues arise
Solution Approach 1:
By stacking identical transistor types uniformly, the patent creates consistent thermal characteristics throughout the stacked structure. This homogeneity allows for better thermal management and reduces thermal budget issues that would arise from alternating different component types with different thermal properties, while still achieving high component density
3Device complexity
If overlapping gate regions are used in stacked layers, then interconnection complexity is reduced, but lateral offset configurations are required for source/drain electrodes
Solution Approach 1:
The patent applies segmentation by laterally offsetting the source/drain electrodes of different stacked layers relative to each other. This segmentation physically separates the electrodes of upper and lower transistor layers, enabling independent electrical connections and simplifying interconnection design while maintaining the overlapping gate region configuration for compactness
Data Source
AI summary
According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.