Self-Aligned Gate Stack with Conformal Cap for Flash Memory
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Solution Overview
Problem
Conventional flash memory cell manufacturing processes face issues with uneven conductive material thickness and damage to dielectric layers, leading to variations in gate widths and channel lengths, which degrade performance and reliability.
Innovation Solution
A method involving the formation of gate stack layers with conformal deposition of a conductive material layer and a cap layer, followed by selective etching to create self-aligned conductive structures with uniform widths, preventing misalignment and protecting dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization and etching back processes are used to deposit conductive material, then the conductive material can cover the stack gates, but the thickness of the conductive material becomes uneven and the dielectric layer is damaged
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before depositing the conductive material. The mandrel is deposited conformally on the side surfaces of the gate stacks, providing a template that guides subsequent material deposition. This preliminary structure ensures uniform thickness distribution and prevents direct contact between etching processes and the dielectric layer, thereby avoiding damage.
Solution Approach 2:
The mandrel structure serves as an intermediary element between the gate stacks and the conductive material. It mediates the deposition process by providing a conformal surface that ensures uniform material distribution. The mandrel also acts as a protective intermediary during etching processes, preventing the dielectric layer from direct exposure to harmful etchants.
2Ease of manufacture
If photolithographic process is used to pattern conductive material, then the select gates can be formed, but misalignment occurs causing large variation in gate widths and channel lengths
Solution Approach 1:
The patent employs self-service through self-aligned fabrication processes. The mandrel structure and subsequent conductive material deposition are performed in a self-aligned manner, where each layer automatically aligns with the previous layer without requiring separate photolithographic alignment steps. This eliminates misalignment issues and ensures consistent gate widths and channel lengths.
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional conformal deposition. Instead of using photolithographic patterns in the horizontal dimension, the invention uses vertical conformal deposition on the side surfaces of gate stacks. This dimensional change from 2D planar processing to 3D conformal coating eliminates alignment errors inherent in photolithography.
3Productivity
If continuous reduction in flash memory cell size is pursued, then higher integration is achieved, but variations in channel length increase and reliability decreases
Solution Approach 1:
The patent applies parameter changes by transitioning from planar geometry to three-dimensional vertical structures. The gate stacks and conductive materials are formed with controlled thickness parameters through conformal deposition, enabling precise control of critical dimensions. This allows continued scaling of memory cell size while maintaining uniform channel lengths and improving reliability through better dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniformity in gate structures, reduces channel length variations, and protects dielectric layers, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers
Implementation Method 2
Then, a cap layer is deposited to conformally cover the conductive material layer
Data Source
AI summary
A method for manufacturing a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, wherein each of the gate stack layers includes a top surface and two side surfaces. A conductive material layer is deposited to conformally cover the top surface and the two side surfaces of each of the gate stack layers. Then, a cap layer is deposited to conformally cover the conductive material layer. Finally, the cap layer and the conductive material layer above the top surface of each of the gate stack layers are removed to leave the cap layer adjacent to the two side surfaces of each of the gate stack layers and covering a portion of the conductive material layer.