Stressed Semiconductor Device for Non-Volatile Memory
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Solution Overview
Problem
In non-volatile memory (NVM) devices, charge leakage from the charge storage layer to the channel region leads to degradation of memory states, which is mitigated by increasing the thickness of the tunnel dielectric, but this requires higher programming and erasing voltages, increasing power consumption and reducing memory array efficiency.
Innovation Solution
A split-gate NVM cell with a tensile stressor layer is introduced, providing longitudinal tensile stress and vertical compressive stress to the charge storage layer and channel region, increasing the energy barrier and effective mass of nanocrystals, thereby reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the tunnel dielectric is increased to reduce charge leakage, then data retention is improved, but programming and erasing voltages must be increased, leading to higher power consumption
Solution Approach 1:
The patent introduces a stressor layer that applies mechanical stress to the tunnel dielectric, changing its physical parameters (band structure, effective mass) to reduce leakage current. This allows maintaining thin dielectric thickness while improving data retention without requiring higher programming voltages, thus resolving the contradiction between reliability and power consumption
Solution Approach 2:
The stressor layer acts as an intermediary element between the charge storage layer and the control gate. It modifies the electrical characteristics of the tunnel dielectric through mechanical stress, enabling reduced leakage current without increasing dielectric thickness or programming voltage, thereby solving the power consumption issue while maintaining data retention
2Stability of the object's composition
If the thickness of the tunnel dielectric is increased to prevent charge leakage, then memory state stability is improved, but the memory array area efficiency is reduced due to larger device footprint
Solution Approach 1:
By applying mechanical stress through the stressor layer, the patent changes the energy barrier parameters of the tunnel dielectric to reduce leakage current. This enables using thinner dielectric layers that occupy less area while maintaining memory state stability, thus resolving the contradiction between stability and area efficiency
3Quantity of substance
If higher programming voltages are applied to program through thicker tunnel dielectric, then charge storage capability is improved, but charge pumps are required, increasing device complexity
Solution Approach 1:
The stressor layer modifies the band structure and reduces the effective barrier height of the tunnel dielectric through mechanical stress. This enables efficient charge tunneling at lower voltages, improving charge storage capability without requiring complex charge pump circuits, thus resolving the contradiction between charge storage capability and device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stressor layer enhances data retention by reducing leakage current from the charge storage layer to the channel region, improving memory performance without increasing power consumption.
Implementation Method 1
a tensile stressor layer for providing a stress to the charge storage layer and to the channel region
Data Source
AI summary
A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.