3D Nanosheet Transistors With Different Doping Profiles
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors beyond single-digit nanometer nodes, particularly in creating three-dimensional (3D) integrated circuits with multiple transistor planes having different threshold voltages, which complicates chip design and power management.
Innovation Solution
A method of microfabrication involving the formation of nanosheet stacks with different doping profiles to create gate-all-around field-effect transistors (GAA FETs) with varying threshold voltages, enabling the growth of multiple transistor planes with distinct characteristics for both high voltage (HV) and low voltage (LV) devices, allowing for optimized performance and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 2D fabrication techniques are used to scale transistors, then transistor density per unit area increases, but scaling challenges intensify at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-stacked nanosheet transistors. Multiple nanosheet stacks are formed at different planes (first plane, second plane, third plane) on the substrate, enabling transistors to be arranged in three dimensions rather than confined to a single plane. This dimensional change increases transistor density by utilizing vertical space while avoiding the scaling limitations of 2D fabrication at single-digit nanometer nodes.
2Adaptability or versatility
If multiple transistor planes with different threshold voltages are created, then chip performance and power efficiency are optimized, but fabrication process complexity increases
Solution Approach 1:
Different nanosheet stacks are formed with distinct doping profiles tailored to specific regions. The first nanosheet stack has a first doping profile, the second nanosheet stack has a second doping profile, and the third nanosheet stack has a third doping profile. These localized quality variations enable different threshold voltages in different transistor planes, allowing optimization for specific chip functions (e.g., high-performance vs. low-power regions) while managing fabrication complexity through systematic process design.
Solution Approach 2:
The fabrication process is segmented into distinct stages for forming different nanosheet stacks at different planes. Each nanosheet stack formation is treated as a separate module with its own doping profile and processing parameters. This segmentation allows independent optimization of each transistor plane's characteristics while maintaining overall process manageability through modular fabrication steps.
3Quantity of substance
If 3D integration is implemented to overcome scaling limitations, then transistor density in volume increases, but application to random logic designs becomes substantially more difficult
Solution Approach 1:
The patent creates a universal 3D nanosheet transistor platform that can accommodate various logic design requirements. By forming multiple nanosheet stacks with different doping profiles on the same substrate, the structure can be configured for different logic functions (e.g., NAND, NOR, flip-flops) and different performance requirements (high-speed, low-power) within a single fabrication process. This multi-functionality makes 3D integration applicable to random logic designs while maintaining ease of manufacture through a unified process approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of transistors with multiple threshold voltages across a substrate, facilitating chip designs with both HV and LV devices, improving performance and power efficiency by allowing for tailored transistor characteristics in both horizontal and vertical directions.
Implementation Method 1
etching unmasked portions of the first nanosheet stack down to a predetermined depth
Implementation Method 2
growing a second nanosheet stack on the substrate in regions of the substrate that have been etched
Data Source
AI summary
Three-dimensional integration can overcome scaling limitations by increasing transistor density in volume rather than area. To provided gate-all-around field-effect-transistor devices with different threshold voltages and doping types on the same substrate, methods are provided for growing adjacent nanosheet stacks having channels with different doping profiles. In one example, a first nanosheet stack is formed having channels with first doping characteristics. Then the first nanosheet stack is etched, and a second nanosheet stack is formed in plane with the first nanosheet stack. The second nanosheet stack has channels with different doping characteristics. This process can be repeated for additional nanosheet stacks. In another example, the formation of the nanosheet stacks with channels having different doping characteristics is performed by restricting layer formation to predefined locations using a patterned layer (e.g., a conformal oxide layer) that limits epitaxial growth to exposed regions of the substrate where the patterned layer is etched away.