FinFET Decoupling Capacitor Gate Leakage Reduction

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Solution Overview

Problem

Conventional metal-oxide-semiconductor capacitors (MOSC) experience high gate leakage, which is undesirable in semiconductor devices, and their capacitance decreases significantly when scaled down.

Innovation Solution

A fin field-effect transistor (FinFET) is used as a decoupling capacitor, featuring a semiconductor fin between isolation regions with a gate stack wrapping around it, reducing gate leakage and maintaining capacitance even at smaller sizes by eliminating potential difference between the gate and substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional MOSC is used as a decoupling capacitor, then the device can provide capacitance for decoupling circuits, but it experiences high gate leakage which is undesirable

Engineering Contradiction:
Improvegate leakageVSAvoidgate leakage current
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent inverts the conventional MOSC configuration by using the FinFET structure where the channel is formed vertically rather than horizontally. This structural inversion allows the device to function as a capacitor while eliminating the gate leakage issue that plagues conventional MOSCs, as the FinFET's vertical channel configuration prevents the formation of leakage paths between gate and substrate.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the physical and geometric parameters of the transistor structure from a planar configuration to a FinFET configuration with vertical fins. This parameter change transforms the device characteristics, allowing it to maintain capacitance while reducing gate leakage by altering the electric field distribution and charge carrier movement paths.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If the MOSC is scaled down to smaller sizes, then the device area is reduced, but the capacitance decreases significantly

Engineering Contradiction:
Improvecapacitor areaVSAvoidcapacitance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from a two-dimensional planar MOSC structure to a three-dimensional FinFET structure with vertical fins extending upward from the substrate. This dimensional change allows the capacitor to maintain or increase its effective area and capacitance even when the footprint on the substrate is reduced, as the vertical dimension provides additional capacitance-generating surface area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The FinFET structure effectively nests multiple capacitance-generating surfaces within a compact footprint. The vertical fins create multiple interfaces between the gate and channel regions, allowing the device to pack more capacitance into a smaller overall area, similar to how nested dolls maximize space utilization.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The FinFET significantly reduces gate leakage while maintaining or increasing capacitance compared to conventional MOSC, especially at smaller scales, providing a more favorable ratio of leakage current to capacitance.

Implementation Method 1

A fin field-effect transistor (FinFET) is used as a decoupling capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9064720B2Decoupling capacitor for FinFET compatible process
Publication Date: 2015.06.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9064720B2 patent drawing
  • US9064720B2 patent drawing
  • US9064720B2 patent drawing

AI summary

A decoupling capacitor formed from a fin field-effect transistor (FinFET) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail.