Vertical Transistor OTP Device with Localized Gate Dielectric Breakdown
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Solution Overview
Problem
Conventional one-time-programmable (OTP) anti-fuse devices with a single metal oxide semiconductor (MOS) transistor face challenges in accurately determining gate dielectric breakdown due to random breakdown locations, leading to variations in sensed current, making it difficult to reliably determine programming logic states.
Innovation Solution
The method involves forming oppositely doped bottom source/drain regions with a high-k dielectric layer directly on the p-type source/drain region in a vertical CMOS inverter structure, where the gate dielectric is positioned directly on the boron doped silicon germanium (SiGe:B) source/drain region, enhancing the breakdown reliability for programming logic states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate dielectric breakdown is used for programming in conventional 1T anti-fuse devices, then programming capability is achieved, but breakdown location randomness causes large current variations making logic state determination difficult
Solution Approach 1:
The patent introduces a bottom spacer layer that creates a localized region with different properties (direct gate dielectric contact) at the bottom source/drain region, while other regions maintain conventional structure. This local structural modification ensures breakdown occurs at a specific location rather than randomly throughout the device, resolving the contradiction between achieving breakdown-based programming and maintaining reliable logic state detection
Solution Approach 2:
The bottom spacer layer is formed in advance during manufacturing, pre-positioning the breakdown location at the bottom source/drain region before programming occurs. This preliminary structural preparation ensures that when programming is performed, the breakdown will occur at the predetermined location with consistent characteristics, improving both programming reliability and measurement precision
2Manufacturing precision
If bottom spacer layer is formed on all source/drain regions, then manufacturing consistency is improved, but breakdown control precision is reduced
Solution Approach 1:
The patent removes the bottom spacer layer from specific regions (n-type source/drain regions) while maintaining it in other regions (p-type source/drain regions). This selective removal extracts the spacer layer from locations where direct contact is desired for breakdown control, while preserving it in locations where structural consistency is beneficial, thus resolving the contradiction between manufacturing consistency and breakdown location control
Solution Approach 2:
The patent creates an asymmetric structure where bottom spacer layers are present on p-type source/drain regions but absent on n-type source/drain regions. This asymmetric configuration allows different functional optimizations in different parts of the device, enabling precise breakdown location control at the p-type region while maintaining overall manufacturing consistency through the systematic asymmetric design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and accurate programming by creating a weak point for gate dielectric breakdown, allowing for precise determination of logic states through controlled voltage application, improving the reliability of OTP devices.
Implementation Method 1
A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region
Implementation Method 2
forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate, forming a first bottom source/drain region at sides of a first fin of the plurality of fins in a first transistor region, and forming a second bottom source/drain region at sides of a second fin of the plurality of fins in a second transistor region. The first and second bottom source/drain regions are oppositely doped. In the method, a bottom spacer layer is formed on the first and second bottom source/drain regions, and the bottom spacer layer is removed from the second bottom source/drain region. A high-k dielectric layer is formed on the bottom spacer layer in the first transistor region, and directly formed on the second bottom source/drain region in the second transistor region. The method also includes forming a gate conductor on the high-k dielectric layer.