Stitched Dies with EMIB Interconnects for High Bandwidth
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Solution Overview
Problem
The challenge in the semiconductor industry is to achieve high bandwidth and capacity while maintaining miniaturization and performance, particularly in scaling multi-gate and nanowire transistors, where lithographic processes face constraints due to the trade-off between feature dimension and spacing, and conventional packaging approaches are inefficient for die-to-die interconnects.
Innovation Solution
The implementation of stitched dies with high bandwidth and capacity, utilizing conductive interconnections to couple dies separated by scribe lines, enabling efficient memory stitching and interposer partitioning for miniaturization, and the use of embedded multi-die interconnect bridges (EMIBs) for fine die-to-die interconnects, which allows for the combination of 2D and 3D connections and integration of DRAM technologies with high-performance interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging approaches are used for die-to-die interconnects, then packaging simplicity is maintained, but bandwidth and capacity are insufficient
Solution Approach 1:
The patent divides the interconnect architecture into multiple segments: embedded interconnect bridges (EMIBs) for fine-pitch die-to-die connections, scribe line interconnects for coarse-pitch connections, and package interconnects for external connections. This segmentation allows each segment to be optimized for its specific function, achieving high bandwidth and capacity without requiring complete redesign of the entire packaging system.
Solution Approach 2:
The patent transitions from traditional 2D planar interconnect architectures to 3D embedded interconnect bridges that extend vertically through the package. The EMIBs are embedded within the package substrate, creating multiple interconnection layers that enable high-bandwidth paths in the vertical dimension, thereby increasing capacity without proportionally increasing footprint area.
2Quantity of substance
If feature dimensions are reduced to increase device density, then capacity increases, but lithographic process constraints worsen due to the trade-off between critical dimension and spacing
Solution Approach 1:
The patent segments the interconnect function across different spatial scales: EMIBs handle fine-pitch connections with pitch of 20-100 micrometers, scribe line interconnects handle intermediate pitch connections, and package interconnects handle coarse-pitch external connections. This multi-scale segmentation allows the lithographic process to work at relaxed pitch dimensions while still achieving high effective density through the combination of multiple interconnect types.
Solution Approach 2:
The patent introduces package substrate interconnect bridges as intermediary structures that mediate between fine-pitch die interconnects and coarse-pitch package connections. These EMIBs act as intermediate connection points that can be formed with relaxed lithographic precision while still enabling high-density interconnect patterns on the dies themselves.
3Quantity of substance
If multi-gate and nanowire transistors are scaled down to increase integration, then functional unit density increases, but short channel control and mobility improvement become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D transistor gates to three-dimensional multi-gate structures (such as tri-gate or gate-all-around nanowire configurations). By adding vertical dimensions to the gate structure, the effective gate control area increases proportionally to the square of the channel width, thereby maintaining strong short-channel control even as horizontal feature dimensions are scaled down to increase density.
Data Source
AI summary
Stitched dies having high bandwidth and capacity are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer, wherein the first device layer is a logic device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the first die by a scribe region. The second device layer is a transistor device layer, and the second plurality of metallization layers includes a layer of capacitor structures between an upper metallization layer portion and a lower metallization layer portion. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies.