Double Mesh MuGFET for Compact Packing Density
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Solution Overview
Problem
The existing technologies for forming multiple gate field-effect transistors (MuGFETs) face challenges in achieving efficient electrical connections and small device sizes due to limitations in modern lithography equipment, leading to large contact geometries and reduced packing density.
Innovation Solution
A double mesh array structure is used, where a first mesh of silicon fins is formed with an oxide layer, and a second conductive mesh is overlaid offset from the first, allowing for electrical isolation and forming source, drain, and gate regions, with contacts created at intersections to achieve a compact and customizable MuGFET device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used to form MuGFET devices, then manufacturing processes are well-established, but device size is large and packing density is reduced
Solution Approach 1:
The patent transitions from planar 2D contact geometry to 3D vertical contact structures by forming contacts that extend through multiple layers and intersect with mesh structures in three dimensions. This dimensional change allows smaller device footprints while maintaining electrical connection integrity, directly resolving the contradiction between reduced device size and maintained manufacturing feasibility.
Solution Approach 2:
The patent implements nested structures where contacts are formed within and through multiple layered meshes, with inner contacts nested within outer contact structures. This nesting approach enables compact device geometry with improved packing density while maintaining established manufacturing processes for forming each individual contact layer.
2Productivity
If contact geometry is reduced to increase packing density, then device size decreases, but electrical connection efficiency deteriorates
Solution Approach 1:
The patent divides the contact structure into multiple discrete contact regions formed at different locations and orientations within the mesh assembly. Each contact segment provides independent electrical connection pathways, so that even if individual contacts are small, the cumulative effect maintains high electrical connection efficiency while achieving high packing density through distributed contact geometry.
Solution Approach 2:
The patent creates three-dimensional contact networks that extend vertically through multiple mesh layers, transforming 2D contact surfaces into 3D contact volumes. This dimensional transformation increases the effective contact area and electrical connection efficiency without increasing the device's planar footprint, thereby maintaining high packing density.
3Area of stationary object
If mesh structures are used to form contacts, then contact areas are enlarged, but device geometry becomes less compact
Solution Approach 1:
The patent employs thin mesh structures that provide large effective contact areas through their extended geometry, yet maintain minimal volume occupation because the meshes are formed as thin films or layers. The mesh wires or traces extend over large areas but with negligible thickness, enabling large contact areas without proportionally increasing device volume.
Solution Approach 2:
The patent utilizes vertical stacking of multiple mesh layers to achieve large total contact area while maintaining compact planar footprint. By distributing contact areas across multiple vertical layers rather than expanding in a single plane, the device achieves enlarged contact geometry without proportional increases in overall device volume.
Data Source
AI summary
A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, at least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least on fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh.