Flash Memory Channel Contact Schottky Barrier Leakage Current
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Solution Overview
Problem
Conventional 3D NAND flash memory devices face challenges due to leakage current issues and manufacturing incompatibility with logic circuits, making it difficult to integrate 3D NAND and advanced CMOS logic circuits on the same silicon substrate.
Innovation Solution
A flash memory device and manufacturing method that form a channel structure with a Schottky contact using a channel layer with opposite conduction types, reducing leakage current and allowing integration with logic circuits by eliminating the need for substrate doping, enabling compatibility with both silicon substrates and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D NAND flash memory devices are manufactured before BEOL process with substrate doping to form source and drain electrodes, then the bottom transistor can be formed with gate select line control, but the manufacturing process becomes incompatible with logic circuits and thermal cycles alter logic transistor characteristics
Solution Approach 1:
The patent extracts the doping process from the manufacturing flow, eliminating the need for substrate doping to form source and drain electrodes. Instead, a doped dielectric layer is used, which can be formed after BEOL processes without affecting logic circuit transistors, thus resolving the compatibility issue while maintaining transistor functionality
Solution Approach 2:
The patent introduces a doped dielectric layer as an intermediary structure to replace the traditionally doped silicon substrate for forming source and drain electrodes. This intermediary layer provides the necessary electrical characteristics without requiring substrate modification, enabling compatibility with both 3D NAND and logic circuit manufacturing processes
2Ease of manufacture
If 3D NAND flash memory devices are manufactured separately from logic circuits on different silicon substrate areas, then the manufacturing process can be completed, but integration of 3D NAND and advanced CMOS logic circuits on the same substrate becomes difficult
Solution Approach 1:
The patent creates a universal manufacturing process that can form both 3D NAND flash memory devices and logic circuits on the same silicon substrate. The modified process using doped dielectric layers instead of substrate doping is compatible with both device types, enabling full substrate utilization and integration
Solution Approach 2:
The patent performs preliminary actions by forming the doped dielectric layer and source/drain structures before completing the BEOL processes for logic circuits. This sequencing allows subsequent logic circuit fabrication without thermal damage, enabling integrated manufacturing of both 3D NAND and CMOS logic on the same substrate
3Productivity
If thermal cycles are added to silicon substrate for 3D NAND process flow, then 3D NAND structures can be formed, but characteristics of logic transistors are inevitably altered
Solution Approach 1:
The patent performs all 3D NAND structure formation steps, including those requiring thermal cycles, before completing the BEOL processes for logic circuits. This preliminary action ensures that logic transistors are not exposed to damaging thermal cycles, preserving their characteristics while still enabling 3D NAND fabrication
Solution Approach 2:
The patent extracts the 3D NAND manufacturing process from the traditional pre-BEOL timing and relocates it to occur after logic circuit transistors are formed but before BEOL completion. This timing extraction allows thermal processes to be applied to 3D NAND structures without affecting already-formed logic transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and facilitates the integration of 3D NAND with logic circuits on the same substrate, enhancing performance and compatibility with BEOL processes.
Implementation Method 1
a channel contact component connecting to the second component of the channel layer, wherein the channel contact component and the second component of the channel layer form a Schottky contact
Data Source
AI summary
A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.