Non-volatile Memory Cell With Segmented Read Program Erase Regions
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Solution Overview
Problem
Conventional non-volatile memory cells face degradation in electrical characteristics due to shared active regions during multiple programming/read/erase operations, limiting their cycle endurance without encountering errors.
Innovation Solution
A non-volatile memory cell structure with separate devices for read, program, and erase operations, where the read device is electrically connected to a coupling device, the floating gate device is connected to a program device, and the erase device is connected to both, with independent operation of the read and program devices, allowing for separate read, program, and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the read device and program device share a common active region, then the device complexity is reduced, but the reliability deteriorates due to cumulative degradation from multiple operations
Solution Approach 1:
The patent divides the memory cell into separate active regions: a first active region for the read device and a second active region for the program device. This segmentation prevents the cumulative degradation that occurs when devices share a common active region, thereby improving reliability while maintaining acceptable device complexity.
Solution Approach 2:
The read device is extracted from the shared active region and placed in a dedicated first active region. This separation removes the read device from the degradation pathway caused by program and erase operations, allowing the program device to operate independently in the second active region without affecting read operations.
2Reliability
If separate devices are used for read, program, and erase operations, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The memory cell structure is segmented into distinct functional regions: a first active region containing the read device, a second active region containing the program device, and a third active region containing the erase device. Each device operates independently in its own region, improving reliability through isolation from degradation effects while maintaining a systematic and organized device layout.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional integration to accommodate multiple separate devices within a compact footprint. By organizing devices in different active regions that can be stacked or arranged in three-dimensional space, the patent achieves high reliability through device separation without proportionally increasing the planar area or overall device complexity.
Data Source
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AI summary
A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.