Semiconductor Bit Line Orthogonal Insulation

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Solution Overview

Problem

The increasing demand for smaller, faster, and more functional semiconductor devices poses challenges in designing semiconductor devices with higher aspect ratios of conductive patterns, requiring innovative solutions to enhance integration and performance while maintaining cost-effectiveness.

Innovation Solution

A semiconductor device design featuring a substrate with a cell array region and peripheral circuit region, utilizing a multi-layer insulating pattern structure with non-metal and metal-based dielectric materials, and a direct contact conductive pattern connected to bit lines, which extends orthogonally to the insulating pattern, allowing for efficient integration and performance enhancement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the aspect ratio of conductive patterns is increased to enhance integration, then device functionality is improved, but the necking phenomenon and bending of bit lines occur

Engineering Contradiction:

ImproveintegrationVSAvoidnecking phenomenon and bending

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a third vertical dimension by stacking insulating patterns (first insulating pattern 112A, second insulating pattern 112B, third insulating pattern 114) above the substrate plane. This vertical stacking allows bit lines to extend orthogonally while maintaining proper spacing and electrical connections, effectively resolving the necking and bending issues that occur in planar configurations by utilizing spatial dimensionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite insulating structures combining multiple dielectric materials with different properties. The first insulating pattern uses a non-metal based dielectric material, while the second and third insulating patterns use metal-based dielectric materials with higher dielectric constants. This composite approach optimizes both electrical performance and structural stability for high aspect ratio conductive patterns.

Inventive Principle:

Principle #40Composite materials

2Area of moving object

If smaller device dimensions are used to reduce size, then device footprint is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvedevice footprintVSAvoidconductive pattern dimensions

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

By moving insulating structures to the vertical dimension through stacking, the patent reduces the lateral footprint of the device while maintaining adequate spacing between conductive elements. The vertical stacking of insulating patterns allows compact planar layout without compromising manufacturing precision, as the critical dimensions are controlled in the vertical rather than lateral direction.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Speed

If higher dielectric constant materials are used to improve electrical performance, then device speed is improved, but process complexity increases

Engineering Contradiction:

Improvedevice speedVSAvoidinsulating pattern structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent applies different dielectric materials strategically in different vertical layers and regions. The second insulating pattern 112B and third insulating pattern 114 use metal-based dielectric materials with higher dielectric constants specifically where needed for electrical performance, while the first insulating pattern 112A uses a non-metal based dielectric material. This localized application of high-k materials improves device speed without requiring all insulating structures to use complex high-k materials.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the integration and performance of semiconductor devices by enabling higher aspect ratios of conductive patterns, reducing the necking phenomenon, and preventing bending of bit lines, thus enhancing the overall efficiency and reliability of the semiconductor device.

Implementation Method 1

The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS10332831B2Semiconductor device including a bit line

Publication Date: 2019.06.25 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.