Heterojunction Bipolar Transistor Layout with Redistribution Layers
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Solution Overview
Problem
Conventional flip-chip technology for HBT device packaging limits the minimum die size due to minimum distance between copper pillars and results in low uniformity of copper pillar height, leading to inefficient heat dissipation and reduced packaging yield.
Innovation Solution
A layout structure incorporating redistribution layers (RDL) and copper pillars with a dielectric material of low dielectric coefficient to improve planarization and flexible layout design, allowing for reduced height difference between emitter and collector copper pillars, and positioning of passive devices to optimize die space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional flip-chip technology is used to dispose copper pillars on HBT electrodes, then heat dissipation efficiency is improved, but the minimum distance between copper pillars limits die size reduction and creates wasteful space
Solution Approach 1:
The patent introduces a redistribution layer (RDL) structure that redistributes copper pillars in a different spatial arrangement, allowing emitter and collector copper pillars to be positioned closer together by changing the conventional direct-electrode mapping geometry to a redistributed network topology
Solution Approach 2:
The redistribution layer acts as an intermediary between the copper pillars and the HBT electrodes, enabling flexible routing and positioning of electrical connections while allowing copper pillars to be placed at optimized locations for heat dissipation and minimal die size
2Manufacturing precision
If conventional flip-chip technology is used to dispose copper pillars, then emitter and collector copper pillars can be formed, but great height difference between emitter and collector epitaxial layers leads to low uniformity of copper pillar height
Solution Approach 1:
The patent applies a planarization process before forming the copper pillars to pre-level the surface, compensating for the height difference between emitter and collector epitaxial layers in advance, so that copper pillars of different heights can be formed uniformly on the planarized surface
Solution Approach 2:
The patent changes the surface topology parameter by applying planarization, transforming the non-uniform surface with great height differences into a uniform surface, which enables consistent copper pillar formation and improves height uniformity
3Ease of manufacture
If minimum distance between copper pillars is maintained in conventional flip-chip technology, then manufacturing is simplified, but wasteful space between copper pillars increases die size
Solution Approach 1:
The redistribution layer enables copper pillars to be positioned in a redistributed pattern that reduces the minimum distance between them by changing the spatial mapping from direct electrode alignment to optimized routing geometry
Data Source
AI summary
A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.