Dummy Floating Gate Electrode Potential Uniformity
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Solution Overview
Problem
Conventional semiconductor devices with non-volatile memory experience erroneous retention failure determination due to non-uniform distribution of movable ions in the interlayer insulating film caused by differing potentials between the dummy and floating gate electrodes, leading to inaccurate assessment of memory cell transistors, especially near the gate contact region.
Innovation Solution
The semiconductor device design includes a dummy floating gate electrode formed in the gate contact region with a coupling ratio closer to that of the floating gate electrode in the memory cell array region, ensuring uniform potential distribution and preventing charge accumulation, thereby suppressing erroneous retention failure determination by electrically connecting the dummy gate electrode to the word line and using undoped oxide films for interlayer insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy floating gate electrode is formed on the element isolation insulating film in the gate contact region, then processing accuracy of the floating gate electrode is improved, but the coupling ratio becomes greater than 1 causing non-uniform potential distribution
Solution Approach 1:
The dummy floating gate electrode is electrically connected to the word line through a conductor portion, ensuring that both the dummy floating gate electrode and the floating gate electrode maintain the same potential during operations. This eliminates the potential difference that caused non-uniform ion distribution and erroneous retention failure determination.
2Reliability
If the dummy floating gate electrode is formed with high coupling ratio, then charge up at via opening is improved, but movable ions become non-uniformly distributed during baking
Solution Approach 1:
By connecting the dummy floating gate electrode to the word line, the patent ensures equipotential conditions during baking processes. This prevents the non-uniform distribution of movable ions that occurred when the dummy gate had a different potential, thereby eliminating erroneous retention failure determinations while maintaining effective charge up capability.
3Ease of manufacture
If the dummy floating gate electrode is isolated, then fabrication simplicity is maintained, but erroneous retention failure determination occurs in memory cell transistors
Solution Approach 1:
The patent introduces a conductor portion as an intermediary element that electrically connects the dummy floating gate electrode to the word line. This simple additional component eliminates erroneous retention failure determinations without significantly complicating the fabrication process, as the conductor can be formed using standard deposition and patterning techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures uniform distribution of movable ions, preventing erroneous retention failure determination during wafer testing and maintaining accurate data retention across memory cells, even under heat treatment conditions.
Implementation Method 1
The dummy floating gate electrode and the word line are electrically connected to each other
Implementation Method 2
The interlayer insulating film is formed to cover the word line
Data Source
AI summary
In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be superimposed on a dummy element formation region in a two-dimensional view. In a first interlayer insulating film and a second interlayer insulating film covering the memory cell transistor, a contact plug is formed to penetrate the first interlayer insulating film and a via is formed to penetrate a second interlayer insulating film.