Input-Output Interface Circuit Latch-Up Prevention
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Solution Overview
Problem
Input-output interface circuits employing electrostatic protection circuits with resistances and diodes, combined with floating N-well technology, face the challenge of latch-up occurrence, which compromises their electrostatic destruction tolerance and ESD immunity.
Innovation Solution
The solution involves separating the resistance in the electrostatic protection circuit from the resistance in the floating well potential adjusting circuit, ensuring that the parasitic PNP transistor remains off by preventing forward-biasing, and using additional MOS transistors to maintain the floating well potential within safe bounds, thereby preventing latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the resistance in the electrostatic protection circuit commonly serves as a protection resistance in the floating well potential adjusting circuit, then the device complexity is reduced, but latch-up occurs due to forward-biasing of the parasitic PNP transistor
Solution Approach 1:
The patent divides the protection function into two separate resistance elements: a first resistance in the electrostatic protection circuit and a second resistance in the floating well potential adjusting circuit. This segmentation prevents the parasitic PNP transistor from being forward-biased during electrostatic discharge events, thereby avoiding latch-up while maintaining circuit protection functionality.
Solution Approach 2:
The patent extracts the protection resistance function from the floating well potential adjusting circuit by introducing a dedicated first resistance element. This separates the electrostatic protection path from the well potential control path, ensuring that voltage drops during ESD events do not affect the parasitic transistor biasing conditions.
2Reliability
If a voltage higher than VDD is inputted to the input-output pad, then the voltage tolerance is improved by the floating N-well technology, but unnecessary current flows from the input side to the power supply side
Solution Approach 1:
The patent introduces a diode element as an intermediary component in the electrostatic protection circuit. This diode is configured to conduct when excessive voltage is applied to the input-output pad, providing a controlled path for transient current to flow to the power supply line, thereby protecting the internal circuit while managing current flow appropriately.
3Device complexity
If the potential on the N-well region is fixed at VDD, then the circuit composition is simplified, but the electrostatic destruction tolerance is reduced when excessive voltage is applied
Solution Approach 1:
The patent implements a dynamic well potential control mechanism where the N-well potential is not fixed but is instead adjusted based on operating conditions. The floating well potential adjusting circuit modifies the well potential adaptively, allowing the circuit to maintain optimal protection characteristics across different voltage conditions while preventing parasitic diode conduction during ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents latch-up in input-output interface circuits, enhancing their electrostatic protection and ESD immunity, leading to a more reliable integrated circuit device and electronic apparatus.
Implementation Method 1
an electrostatic protection circuit that protects an internal circuit from electrostatic destruction, when an excessive voltage is applied to an input-output pad (a common terminal for signal input and signal output), by circulating a transient current to a power supply line or a ground line via a resistor and a diode
Implementation Method 2
when an excessive electrostatic surge or the like exceeding the VDD is applied to the source of the PMOS transistor, a parasitic diode present between its source (P-type impurity region) and the N-well is prevented from turning on, thereby preventing a large transient current from flowing in the power supply line (VDD line) through the parasitic diode
Implementation Method 3
by circulating a transient current to a power supply line or a ground line via a resistor and a diode
Data Source
AI summary
An input-output interface circuit of the present invention includes an input-output terminal, an input buffer, a first MOS transistor of a first conductivity type formed in a floating well region, an output buffer for outputting a signal externally through the input-output terminal, an electrostatic protection circuit, and a floating well potential adjusting circuit, wherein the electrostatic protection circuit has a first resistance, and a diode connected between another end of the first resistance and a high level power supply potential, and the floating well potential adjusting circuit has a second resistance having one end connected to the input-output terminal, and a second MOS transistor of the first conductivity type having one end connected to another end of the second resistance, another end connected to the floating well region, and a gate connected to the high level power supply potential.