Oxide Semiconductor Memory Latch Circuit Leakage Reduction
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Solution Overview
Problem
Latch circuits in memory devices have high power consumption due to multiple paths of leakage current between power supply and ground potentials, leading to increased energy usage and larger device area, and they contain a large number of transistors.
Innovation Solution
A memory device design utilizing oxide semiconductor and silicon transistors, where only one path of leakage current exists between the power supply and ground potentials, reducing power consumption and device area, and incorporating a comparator and output potential determiner to manage signal potentials, thereby minimizing the number of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a latch circuit is used in a memory device, then data storage function is achieved, but power consumption increases due to multiple leakage current paths
Solution Approach 1:
The patent extracts and eliminates redundant leakage current paths from the latch circuit by carefully designing the transistor connections and clock signal distribution, keeping only one necessary leakage path while removing others that contribute to power consumption
Solution Approach 2:
The patent changes the operational parameters of the latch circuit by using complementary clock signals (CLK and CLKB) to control transistor switching, thereby reducing the number of simultaneous conduction paths and minimizing leakage current
2Reliability
If a latch circuit with multiple transistors is used, then data storage capability is provided, but device area increases
Solution Approach 1:
The patent merges the functionality of multiple transistors into a more compact configuration where transistors serve dual purposes in different operational phases, reducing the total transistor count while maintaining latch functionality
Solution Approach 2:
The patent designs transistors to perform multiple functions - serving as both storage elements and switching elements at different clock phases, thereby reducing the overall number of transistors needed for the latch circuit
3Reliability
If a latch circuit with many transistors is implemented, then data holding function is achieved, but the number of transistors increases
Solution Approach 1:
The patent segments the latch circuit operation into distinct phases controlled by complementary clock signals, allowing fewer transistors to perform the data holding function through time-multiplexed operation rather than requiring all transistors to be simultaneously active
Solution Approach 2:
The patent employs periodic clock signals to alternately activate different transistor pairs, enabling the latch to maintain data with fewer transistors by utilizing time-based switching rather than continuous conduction paths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces power consumption, area, and transistor count in memory devices by eliminating redundant leakage paths and optimizing transistor usage, while maintaining data integrity even when power is stopped.
Implementation Method 1
The oxide semiconductor transistor has an advantage of an extremely small leakage current (also referred to as off-state current)
Data Source
AI summary
To reduce power consumption of a memory device. To reduce the area of a memory device. To reduce the number of transistors included in a memory device. The memory device includes a comparator comparing a first output signal with a second output signal, a first memory portion including a first oxide semiconductor transistor and a first silicon transistor, a second memory portion including a second oxide semiconductor transistor and a second silicon transistor, and an output potential determiner determining a potential of the first output signal and a potential of the second output signal. One of a source and a drain of the first oxide semiconductor transistor is electrically connected to a gate of the first silicon transistor. One of a source and a drain of the second oxide semiconductor transistor is electrically connected to a gate of the second silicon transistor.