Field Cut Region Enhances Carrier Mobility in CMOS Isolation
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Solution Overview
Problem
Integrated circuit devices face challenges in increasing operating speed due to parasitic capacitance and limited transistor performance, which hinders the advancement of compact and high-density electronics.
Innovation Solution
The integration of a field cut region in the isolation area between PMOS and NMOS transistors, applying tensile stress to enhance carrier mobility by adjusting the width of isolation film portions, thereby improving transistor performance without adding complex wiring structures or separate processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the isolation region width is increased to reduce parasitic capacitance between transistors, then parasitic capacitance is reduced, but transistor performance and carrier mobility deteriorate
Solution Approach 1:
The patent applies local quality by creating a field cut region with different properties within the isolation region. Specifically, the field cut region has a different doping concentration (higher acceptor concentration) compared to the surrounding isolation region, creating a localized area that provides tensile stress to enhance carrier mobility in the channel while maintaining electrical isolation between adjacent transistors. This resolves the contradiction by making the isolation region non-uniform - the field cut region improves transistor performance locally without compromising the overall isolation function.
2Productivity
If complex wiring structures are added to improve circuit design for increasing operating speed, then circuit performance may be improved, but device complexity and parasitic capacitance increase
Solution Approach 1:
The patent applies self-service by enabling the isolation region itself to provide the function of enhancing carrier mobility through the field cut region. Instead of requiring complex wiring structures or additional components to improve operating speed, the isolation region is designed to inherently provide tensile stress to the channel through its doped field cut region, thus improving transistor performance and operating speed without adding complexity to the circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances carrier mobility and reduces propagation delay, leading to increased operating speed and performance of integrated circuit devices without introducing undesirable parasitic capacitance.
Implementation Method 1
applying tensile stress to enhance carrier mobility by adjusting the width of isolation film portions
Data Source
AI summary
An integrated circuit device includes a substrate including a first conductivity type region and a second conductivity type region, a first active region arranged in the second conductivity type region, a second active region arranged in the first conductivity type region and spaced apart from the first active region with an isolation region between the second active region and the first active region, an isolation film formed in the isolation region, and a first field cut region extending along the isolation region in a first direction parallel with a channel length direction of each of a first conductivity type transistor on the first active region and a second conductivity type transistor on the second active region.