Fin-FET Gate Height Control via Dummy Gate Extraction
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Solution Overview
Problem
The existing methods for fabricating fin field-effect-transistor (Fin-FET) devices face challenges in gate height control and inter-layer dielectric (ILD) control, particularly due to the complexity of processing and manufacturing associated with scaling down feature sizes, which leads to issues like dishing effects and poor control over the gate height.
Innovation Solution
A method involving the formation of a substrate with semiconductor structures, a contact etch stop layer, and an inter-layer dielectric layer, followed by planarization processes to expose and remove portions of the ILD and hard mask layers, ultimately forming gate trenches and metal gates within the Fin-FET device, ensuring precise control over gate height and ILD layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If multiple CMP steps (FOXCMP, HDPCMP, POPCMP) are used to planarize the structure, then the surface flatness is improved, but the dishing effect worsens and gate height control deteriorates
Solution Approach 1:
The patent extracts and removes the dummy gate structure after it has served its purpose as a placeholder and alignment reference. By removing the dummy gate, the need for multiple CMP steps to achieve flatness is eliminated, as the actual gate structure is formed directly in the trench without requiring extensive planarization of underlying layers.
Solution Approach 2:
The patent performs preliminary actions by forming the gate trench and filling it with metal gate material before final planarization. The ILD layer is deposited and partially removed to expose the dummy gate, but the critical gate height is established during the trench formation and metal filling steps, not during subsequent CMP operations.
2Area of moving object
If feature sizes are scaled down to increase integration density, then the device capacity is improved, but the processing complexity worsens
Solution Approach 1:
The patent segments the gate structure formation into distinct phases: dummy gate formation for alignment, gate trench formation through selective removal, and metal gate filling. This segmentation allows each step to be optimized independently, reducing overall processing complexity despite scaled dimensions.
Solution Approach 2:
The dummy gate acts as an intermediary structure that facilitates precise alignment and formation of the actual gate. It serves as a placeholder and reference structure during manufacturing, enabling accurate positioning of subsequent layers without requiring complex alignment procedures at scaled dimensions.
3Ease of manufacture
If Flowable CVD oxide and HDPCVD oxide are deposited followed by multiple CMP steps, then the ILD layer formation is achieved, but the dishing effect and gate height control worsen
Solution Approach 1:
The patent applies local quality by selectively removing portions of the ILD layer to expose the dummy gate in specific regions where gate trenches are needed, while maintaining the ILD layer in other regions. This localized modification allows precise control over where gate structures will form without requiring global planarization of the entire structure.
Data Source
AI summary
First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.