Semiconductor Crystallization via Laser Annealing
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Solution Overview
Problem
Conventional methods for forming high-quality crystalline semiconductor layers on amorphous dielectric layers in the back-end-of-line transistor fabrication process face limitations, such as restricted thermal budgets and challenges in maintaining crystallinity through metal and interlayer dielectric layers.
Innovation Solution
A method involving the formation of a patterned seed layer on the semiconductor layer, followed by thermal annealing to crystallize the semiconductor layer, which allows for self-aligned crystallization and utilization of the crystallized portions as channel regions, while also functioning as a dummy gate for gate replacement processes, compatible with back-end-of-line semiconductor manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional thermal annealing is used to crystallize semiconductor layers, then crystallinity can be improved, but thermal budget is exceeded and existing metal/interlayer dielectric layers are damaged
Solution Approach 1:
The patent replaces conventional thermal annealing with a laser-based crystallization process. The laser provides localized energy to crystallize the semiconductor layer without heating the entire wafer, thus avoiding thermal damage to metal and interlayer dielectric layers while achieving the required crystallinity for device performance
Solution Approach 2:
The invention transitions from bulk thermal processing to localized laser processing, effectively moving from a three-dimensional thermal field to a highly focused energy beam approach. This dimensional change in the energy delivery method allows precise control of the crystallization zone without affecting surrounding structures
2Manufacturing precision
If multiple fabrication steps are used to form crystalline semiconductor layers, then crystallinity can be improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the seed layer formation and crystallization steps into a single integrated process. The amorphous semiconductor layer serves as both the material to be crystallized and the source of crystalline structure, eliminating the need for separate seed layer deposition and subsequent removal steps
Solution Approach 2:
The amorphous semiconductor layer itself provides the crystalline template through its atomic structure, enabling self-directed crystallization. The material serves its own function as both substrate and crystal template, reducing the need for external seed layers and simplifying the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-quality crystalline semiconductor layers with improved crystallinity, reducing manufacturing steps and ensuring compatibility with existing semiconductor processes, thereby enhancing transistor performance.
Implementation Method 1
A crystallization operation is performed on the semiconductor layer using the patterned seed layer as a seed of crystallization, thereby forming a crystallized semiconductor layer
Implementation Method 2
the crystallization operation includes a thermal annealing
Data Source
AI summary
In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.