3D IC Metal-Layer Stacking for Fine-Pitch Vertical Connectivity
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Solution Overview
Problem
The increasing cost of mask sets and limited vertical connectivity in Through-Silicon-Via (TSV) technology hinder the development and scalability of 3D Integrated Circuits (ICs), particularly for custom products with smaller volumes and diverse markets, while on-chip interconnects dominate performance and power consumption.
Innovation Solution
The development of multilayer 3D IC devices with single crystal transistors and advanced bonding techniques, including oxide-to-oxide bonds and metal-to-metal connections, reduces the need for lithography steps and enables vertical connectivity improvements by using smaller connections, such as vias less than one micron in size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon-Via (TSV) technology is used for vertical connectivity, then 3D IC structure is achieved, but vertical connectivity is limited and development costs increase
Solution Approach 1:
The patent divides the vertical interconnection structure into multiple metal layers (first metal layer, second metal layer, third metal layer) with via regions connecting them, replacing the monolithic TSV approach with a segmented metallurgical structure that reduces complexity and costs
Solution Approach 2:
The patent transitions from traditional planar 2D IC architecture to a 3D stacked architecture with multiple metal layers and via regions enabling vertical connectivity between stacked semiconductor wafers, achieving improved vertical connectivity without TSV limitations
2Device complexity
If mask set costs are reduced, then development costs decrease, but manufacturing precision may be compromised
Solution Approach 1:
The patent combines multiple metal layers (first metal layer, second metal layer, third metal layer) and via regions into an integrated interconnection structure that can be formed using fewer lithography steps, reducing mask set costs while maintaining alignment precision through the unified design
Solution Approach 2:
The metal layers serve multiple functions: electrical interconnection, mechanical support, and alignment reference for via formation, reducing the need for separate precision lithography steps and thereby reducing development costs without compromising alignment accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances vertical connectivity and reduces development costs, offering improved yield and reliability for complex 3D ICs, particularly in Application Specific Integrated Circuits (ASICs), while addressing the limitations of TSV technology.
Implementation Method 1
including oxide-to-oxide bonds and metal-to-metal connections
Implementation Method 2
including oxide-to-oxide bonds and metal-to-metal connections
Data Source
AI summary
A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (“IO”) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the “IO”-circuits; the second level is disposed over the first level.