3D IC Semiconductor Package Structure for Higher Yield POP Integration
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Solution Overview
Problem
The existing package-on-package (POP) technology faces challenges in increasing yield due to defects in semiconductors manufactured at low costs, leading to the need for a new semiconductor packaging method that can integrate semiconductors as 3D IC structures without separate fabrication processes, while also reducing the use of encapsulating materials and enhancing package reliability and rigidity.
Innovation Solution
The proposed solution involves fabricating semiconductor packages with a 3D IC structure by stacking individual semiconductors on a front side redistribution layer using through-silicon vias and embedding these structures within an embedded trace substrate, allowing for the integration of system-on-chip (SOC) components as 3D ICs, which reduces the need for separate 3D IC fabrication and minimizes the use of epoxy molding compound.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If individual semiconductors are integrated into a system-on-chip (SOC) using existing POP technology, then integration density is improved, but yield decreases due to defects in low-cost manufactured semiconductors
Solution Approach 1:
The patent segments the semiconductor integration process by distinguishing between different semiconductor types (high-cost new process semiconductors and low-cost old process semiconductors) and integrating them separately rather than forcing them into a single SOC structure. This allows defective low-cost semiconductors to be used in non-critical applications while maintaining high yield.
Solution Approach 2:
The patent applies different integration approaches to different semiconductor types based on their quality characteristics. High-cost semiconductors are integrated into SOCs with strict quality requirements, while low-cost semiconductors are integrated separately or into non-critical SOC functions, optimizing both yield and integration density.
2Area of stationary object
If a system-on-chip (SOC) is used to integrate multiple functions, then package size is reduced, but manufacturing cost increases due to discarding defective semiconductors
Solution Approach 1:
The patent changes the integration parameter from all-or-nothing SOC integration to selective integration, where only certain semiconductors are integrated into the SOC while others are mounted separately. This reduces the penalty for defective semiconductors and lowers manufacturing costs while maintaining compact package size.
3Volume of moving object
If existing POP technology is used with separate 3D IC fabrication processes, then integration is achieved, but the process becomes complex and requires multiple separate fabrication steps
Solution Approach 1:
The patent merges the 3D IC fabrication process with the standard POP packaging process, eliminating the need for separate 3D IC fabrication steps. The through-silicon via formation and chip stacking are integrated into the existing POP workflow, simplifying the overall fabrication process while maintaining 3D integration capabilities.
4Reliability
If extensive encapsulating materials are used in existing POP technology, then chip protection is achieved, but material usage increases and package rigidity decreases
Solution Approach 1:
The patent extracts and removes unnecessary encapsulating materials from the POP structure, retaining only the essential molding compound for chip protection. This reduces material usage and improves package rigidity while maintaining adequate protection through optimized encapsulation design.
5Ease of manufacture
If existing POP technology is used without 3D IC structure integration, then manufacturing is simpler, but integration density and modern performance requirements are not met
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking chips and forming through-silicon vias. This enables high integration density and modern performance requirements to be met while maintaining manufacturing simplicity through integration with the standard POP process.
Data Source
AI summary
A semiconductor package may include: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die and a second semiconductor chip die having through-silicon vias (TSVs), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs; a printed circuit board on the front side redistribution layer and surrounding the 3D IC structure; a molding material on the front side redistribution layer and at least partially encapsulating the 3D IC structure and the printed circuit board; and a back side redistribution layer on the molding material.