3D IC Pad Structure Using TSV Tail Connections
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Solution Overview
Problem
Conventional I/O pad structures designed for single chip packaging are not compatible with 3D integrated circuit technology, as through-silicon-vias and inter-connectors in 3D ICs prevent the placement of I/O cell structures underneath aluminum pads, making it impractical and costly to redesign the pad structure for 3D applications.
Innovation Solution
A through-silicon-via (TSV) tail structure is attached to a conventional I/O pad structure, allowing it to be used in 3D ICs by creating a separate connection between the top metal layer and the substrate, which can function as either a Cu-bond pad or a probe pad, enabling electrical connectivity without requiring redesign of the existing pad structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional I/O pad structure is used in 3D IC, then the existing proven I/O cell structure can be retained, but the through-silicon-vias and inter-connectors prevent placement of I/O cell structures underneath the aluminum pads
Solution Approach 1:
The pad structure is segmented into two distinct types: first pads with I/O cell structures for signal processing, and second pads without I/O cell structures for through-silicon-via connections. This segmentation allows each pad type to serve its specific function independently, resolving the conflict between retaining proven I/O cell structures and enabling 3D IC compatibility.
Solution Approach 2:
Different regions of the pad structure are assigned different qualities and functions. First pads maintain the conventional structure with I/O cell structures for signal processing, while second pads are designed without I/O cell structures to accommodate through-silicon-vias. This local differentiation allows the overall structure to be both reliable and adaptable to 3D IC requirements.
2Adaptability or versatility
If the I/O pad structure is redesigned for 3D IC, then compatibility with 3D IC is achieved, but redesign time and cost increase
Solution Approach 1:
The pad structure is designed with universal compatibility for both conventional and 3D IC applications. By incorporating second pads specifically designed for through-silicon-via connections while maintaining first pads with I/O cell structures, the structure achieves multi-functionality that works across different IC architectures without requiring complete redesign.
Solution Approach 2:
The patent performs preliminary design actions by pre-defining two types of pads with distinct functions before actual 3D IC implementation. The second pads are pre-configured to accommodate through-silicon-vias and inter-connectors, eliminating the need for redesign when transitioning to 3D IC architecture.
3Reliability
If I/O cell structures are placed under aluminum pads, then electrical connectivity is maintained, but through-silicon-vias and inter-connectors cannot be properly formed
Solution Approach 1:
The pad structure is segmented into first pads with I/O cell structures for electrical connectivity and second pads without I/O cell structures for through-silicon-via formation. This segmentation resolves the manufacturing conflict by providing dedicated regions for each function.
Solution Approach 2:
Second pads serve as intermediary structures that facilitate through-silicon-via formation and inter-connector connections without requiring I/O cell structures. These pads act as mediators between the aluminum pads and the through-silicon-vias, enabling proper via formation while maintaining overall electrical connectivity through the inter-connector structure.
Data Source
AI summary
This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.