Semiconductor/Solid-State Device Details TRIZ Cases
- Rotary Traveling Wave Oscillator with Dynamic Direction Reversal
Switchable positive and negative resistance elements let a rotary traveling wave oscillator reverse wave direction in real time without power cycling.
- Substrate Inductor LC Oscillator Layout for Low-Jitter Signal Generation
Substrate conductive lines provide LC oscillator inductance to cut noise-induced jitter and avoid costly thick-metal VCO fabrication.
- Inductive Interposer Layout for MOSFET Feedback Control
An inductive interposer between gate and drain controls mutual inductance and high-frequency feedback in power MOSFET bus layouts.
- IC Chip Gettering Layer for Laser Attack Protection
Metal-impurity gettering in the substrate scatters laser beams, raising fault-injection power without adding circuit overhead or chip area.
- Digitally Controlled Oscillator Using Variable Inductance Tuning
Variable inductance tuning replaces capacitor banks in a DCO to improve frequency resolution, reduce noise sensitivity, and save SoC area.
- Terahertz Oscillator Layout for Horizontal Wave Emission
A MIM reflector, resonator, waveguide, and horn aperture improve horizontal terahertz emission while limiting leakage across a wide band.
- I/O Power Line Layout for Low-Impedance System LSI
Embedding I/O power lines in each I/O cell keeps source connections low impedance while reducing wide power-line area in system LSI layouts.
- III-Nitride HEMT Field Plate Layout for Lower Miller Capacitance
A grounded gate-connected field plate in a III-nitride HEMT cuts Miller capacitance while preserving high-frequency response and simpler fabrication.
- Heated Cooling Element for Frequency Converter Semiconductor Stress
Resistive heating raises the cooling element’s minimum temperature to cut thermal cycling stress and extend frequency converter semiconductor life.
- Grounded Isolation Wire Layout for Dense RF Circuit Blocks
Grounded isolation wires placed between dense circuit blocks suppress electromagnetic coupling and preserve signal integrity in high-frequency layouts.
- Protective Logic Circuit Layout for IC Tamper Detection
Protective lines and logic gates let an IC self-test for probing or physical tampering by checking output responses to test patterns.
- 3D IC Pad Structure Using TSV Tail Connections
A split pad layout adds a TSV tail to conventional I/O pads, preserving proven cell structures while enabling 3D IC interconnection.
- High-Temperature Semiconductor Package With Leakage-Control Circuit Stack
A thermal barrier package and stacked lower-threshold device keep high-temperature semiconductors offloading heat from the PCB while limiting leakage.
- Stacked Memory Layout with Rotational I/O Alignment
Rotationally offset memory chips align matching I/O pads, shortening interconnect paths to cut signal delay and raise stack density.
- On-Chip Identification Circuit Using Random Conductor Shorts
Random shorts from conductor spacing and mask variation create unique on-chip IDs and private keys without fuses or added chip area.
- Wireless Backside Shielding for Chip Attack Detection
Wireless front-to-back chip shielding detects backside breaches through resonant return-signal changes and can reset the IC on attack.
- Display Driving Chip Power Layout for Low Line Resistance Variation
An auxiliary power input placed closer to circuit cells reduces line resistance variation and stabilizes display driving signals.