On-Chip Identification Circuit Using Random Conductor Shorts
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Solution Overview
Problem
Integrated circuit chips require unique on-chip identifiers and private keys, but existing methods using fuses and anti-fuses increase manufacturing costs and chip space, and current cryptography methods are complex and costly.
Innovation Solution
The use of across chip line variations (ACLV) and random mask alignment variations to create pairs of conductors with predetermined distances and widths, resulting in a random chance of shorts or opens, which are used to generate a unique on-chip identifier or private key, reducing chip space and manufacturing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuses and anti-fuses are used to create on-chip identifiers, then unique identification is achieved, but chip space is consumed and manufacturing time increases
Solution Approach 1:
The invention extracts the identification function from traditional fuse-based mechanisms and implements it through inherent process variations in conductor geometry. By removing the need for dedicated fuse structures, chip space is conserved while maintaining unique identification capability through naturally occurring ACLV differences across conductors
Solution Approach 2:
The identification circuit serves itself by utilizing inherent process variations (ACLV) that occur during normal fabrication. Instead of requiring separate programming steps or additional structures, the natural variations in conductor width, thickness, and position automatically generate unique identification patterns for each chip
2Reliability
If fuses and anti-fuses are programmed at test to create identifiers, then unique identification is achieved, but manufacturing time and costs increase
Solution Approach 1:
The identification patterns are established during the fabrication process itself through controlled conductor spacing and inherent ACLV, rather than requiring subsequent programming actions at test. The conductors are positioned at predetermined distances during manufacturing, so that process variations automatically create the identification bits before the chip leaves the fabrication line
Solution Approach 2:
The fabrication process serves dual purposes: creating functional conductors and simultaneously establishing unique identification patterns. The same process steps that form the conductors with specific geometries and spacings also generate the random identification bits, eliminating the need for separate programming operations
3Reliability
If traditional cryptography methods are used to generate private keys, then secure keys are produced, but the process is complicated and costly
Solution Approach 1:
The invention converts harmful process variations (ACLV) that are typically considered defects or sources of yield loss into a beneficial resource for generating secure private keys. The same variations in conductor dimensions and positions that might cause functional issues are harnessed to create unique, unpredictable key material, turning a potential harm into a security advantage
Solution Approach 2:
The chip itself generates its own private key material through inherent physical variations, eliminating the need for external random number generators or complex key generation circuits. The ACLV present in every conductor automatically provides the entropy needed for secure key generation without additional complexity
4Reliability
If conductor pairs are placed close together to increase short probability, then identifier randomness improves, but manufacturing precision requirements increase
Solution Approach 1:
The invention changes the approach from relying on tight tolerances to achieve randomness to using controlled parameter variations within a broader range. By designing conductors with specific width ranges and spacing distributions, the system leverages the natural spread of ACLV across this range to generate randomness, rather than requiring precise control at a single nominal value
Data Source
AI summary
Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.