3D IC Semiconductor Package Using PCB to Replace Backside RDL

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Solution Overview

Problem

The existing package-on-package (POP) technology faces high manufacturing costs due to the need for fine patterning processes in forming redistribution layers, which limits the integration density and efficiency of semiconductor packaging.

Innovation Solution

A semiconductor package is developed using a 3D IC structure with individual semiconductors stacked on a front side redistribution layer and a back side printed circuit board (PCB) replacing the traditional back side redistribution layer, reducing the number of processes and manufacturing costs by eliminating the need for fine patterning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fine patterning processes are repeatedly performed to form front side redistribution layers and back side redistribution layers in package-on-package technology, then redistribution layers can be formed to enable stacking, but manufacturing costs increase and the number of processes increases

Engineering Contradiction:
Improvestacking capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the back side redistribution layer (BRDL) from the package-on-package structure, replacing it with a back side PCB. This removal of the problematic component (BRDL requiring fine patterning) directly reduces manufacturing complexity and cost while preserving the stacking capability through alternative interconnection methods using the PCB and conductive posts.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the expensive and complex back side redistribution layer with a more economical back side PCB solution. The PCB, while serving a different primary function, provides the necessary interconnection capability at lower manufacturing cost, effectively substituting a high-cost component with a lower-cost alternative that achieves the same functional goal.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Adaptability or versatility

If fine patterning processes are repeatedly performed to form redistribution layers, then redistribution layers can be formed for stacking, but the number of processes increases

Engineering Contradiction:
Improvestacking capabilityVSAvoidnumber of processes
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent removes the back side redistribution layer formation process from the manufacturing sequence, eliminating the associated fine patterning steps. This extraction of the problematic process reduces the total number of manufacturing steps while maintaining stacking functionality through the back side PCB and conductive post architecture.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces the back side PCB as an intermediary structure that mediates between the lower semiconductor package and the upper semiconductor package. This intermediary eliminates the need for complex fine patterning processes by providing a pre-fabricated interconnection substrate that simplifies the overall manufacturing process flow.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If system-on-chip integrates multiple semiconductors in one chip, then package size is reduced and power consumption is minimized, but any defective semiconductor causes all other semiconductors to be discarded

Engineering Contradiction:
Improvepackage sizeVSAvoidyield
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent segments the system-on-chip into separate semiconductor chips that can be independently mounted on the front side redistribution layer. This segmentation allows individual chips to be replaced if defective, rather than discarding an entire integrated system-on-chip, thereby improving yield while maintaining compact packaging through vertical stacking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from horizontal integration (system-on-chip) to vertical integration (stacked chips). By arranging multiple semiconductor chips in the vertical dimension rather than integrating them horizontally in a single chip, the system achieves both compact size and improved reliability, as defective chips can be individually replaced without affecting others.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Ease of manufacture

If back side redistribution layer is replaced with back side PCB, then manufacturing cost is reduced and number of processes is reduced, but structural change is required

Engineering Contradiction:
Improvemanufacturing costVSAvoidstructural configuration
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent makes the back side PCB serve multiple functions: it provides mechanical support, electrical interconnection between packages, and thermal management. By making the PCB multi-functional, the design achieves manufacturing simplicity and cost reduction without requiring overly complex structural changes, as the PCB is a standard component that can be adapted to fulfill multiple roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The back side PCB acts as an intermediary structure that simplifies the overall package configuration. By introducing this standard component as a mediator between the lower package and upper package, the design achieves structural simplification and manufacturing ease, trading minimal structural complexity for significant manufacturing benefits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240258274A1Semiconductor packages and method for fabricating the same
Publication Date: 2024.08.01 SAMSUNG ELECTRONICS CO LTD
  • US20240258274A1 patent drawing
  • US20240258274A1 patent drawing
  • US20240258274A1 patent drawing

AI summary

Provided is a semiconductor package including a redistribution layer, a three-dimensional integrated circuit (3D IC) structure on the redistribution layer, a plurality of conductive posts on the redistribution layer adjacent to the 3D IC structure, a molding material on the redistribution layer and encapsulating the 3D IC structure and the plurality of conductive posts, and a printed circuit board (PCB) on the molding material.