3D IC Redundant Die Bypass for Reliability

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Solution Overview

Problem

3D IC packages present challenges in fabrication and verification, as once stacked dies are encapsulated, it is impractical to repair or replace a damaged die, leading to potential system failure without redundancy or fail-safe mechanisms.

Innovation Solution

Incorporating redundant dies and bypass mechanisms within the 3D IC package, where one die can be substituted for another in case of failure, using through-silicon vias and control logic to selectively disconnect or reconnect dies from power and data buses, allowing for round-robin access to ensure continuous operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant dies and bypass mechanisms are incorporated into the 3D IC package, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidpackage complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system is divided into multiple independent dies (primary and redundant) that can be independently controlled. Each die has its own bypass mechanism that can be activated or deactivated separately, allowing selective isolation of failed components while maintaining overall system functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bypass mechanisms are dynamically controllable through control logic that can change the operational state of dies based on detected failures. The system transitions from a static configuration to a dynamic one where redundant dies can be activated when primary dies fail, optimizing reliability without permanently increasing complexity.

Inventive Principle:
Principle #15Dynamics

2Volume of moving object

If through-silicon vias are used to connect stacked dies, then space utilization is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvepackage volumeVSAvoidvia alignment precision
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

Multiple functional layers are nested within the vertical stack, with through-silicon vias passing through entire die thickness to connect conductive patterns on front and back faces. This nesting approach allows compact 3D integration while the vias serve multiple connection purposes across different die layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The system transitions from 2D planar connections to 3D vertical connections using through-silicon vias. This dimensional change enables compact package volume by stacking dies vertically, with vias providing inter-layer connectivity in the vertical dimension rather than requiring lateral extensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of operation

If control logic is added to selectively disconnect dies from power and data buses, then ease of operation is improved, but device complexity increases

Engineering Contradiction:
Improvedie isolation controlVSAvoidcontrol logic complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The control logic receives feedback about die operational status and automatically activates bypass mechanisms when failures are detected. This feedback-driven approach simplifies operation by eliminating manual intervention, as the system self-manages the isolation of failed dies and activation of redundant components.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The bypass mechanisms are self-activating based on failure detection, eliminating the need for external control or manual reconfiguration. The control logic automatically manages power disconnection and data bus isolation when dies fail, allowing the system to service itself without increasing operational complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9100006B23D IC structure and method
Publication Date: 2015.08.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9100006B2 patent drawing
  • US9100006B2 patent drawing
  • US9100006B2 patent drawing

AI summary

An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus.