Programmable Logic Circuit Arrangements TRIZ Cases
- Scannable Dynamic Register With Precharge for Shorter Setup Time
Precharge and scan-enable circuitry shorten dynamic register setup time while adding scan capability without pulsed clock overhead.
- PLD Configuration Bitstream Alignment Using Padding Bits
Removed phantom bits shrink PLD configuration data, while padding bits preserve register alignment and avoid decompression delays.
- Transparent-Latch Dynamic Register for Shorter Setup Times
A precharge circuit and small transparent latch cut setup time in dynamic registers without pulsed clock overhead, while preserving scan mode.
- Reconfigurable Logic Tile for Dynamic ASIC Adaptation
Dynamic logic modules let an ASIC reconfigure functions and interconnections during operation, avoiding rebuilds while preserving speed and area efficiency.
- Programmable PLL Clock Distribution for Multi-Standard Serial Interfaces
A four-channel PMA and shared PLL layout supports multiple serial standards while improving area efficiency and reducing PLD die cost.
- Data Output Driver Strength Switching Across Memory Load Conditions
Selectable pull-up and pull-down pre-drivers vary output strength across voltages and memory chip counts to keep data slew rates consistent.
- Configurable IC Trigger Circuits for Filtered Debug Event Counting
A separate configurable IC debug network detects selected events, counts occurrences, and captures filtered data without burdening the main routing fabric.
- Programmable HSSI Channel Layout With Shared PLLs for Multi-Protocol PLDs
A four-channel HSSI module shares programmable PLL resources to support multiple serial standards while saving PLD die area and cost.
- Structured ASIC Composition for Multi-FPGA Behavior Matching
Interface adapters and CAD stitching combine multiple FPGAs into one structured ASIC while preserving one-to-one behavior and lowering latency.
- PLD Partial Reconfiguration With Fixed Debug Interface
A fixed PLD interface preserves signal visibility during partial reconfiguration, enabling in-system debugging without severed connections.
- FPGA Bitstream Descrambling Using Key-Controlled Multiplexers
Key-controlled multiplexers descramble FPGA configuration bitstreams to protect them with lower circuit area and power than encryption hardware.
- Hybrid Logic Interconnects for Bypassing and Augmenting Hard Blocks
Configurable interconnects route signals between hard and soft logic so hard blocks can be bypassed or extended without losing speed or flexibility.
- Configurable IC Trigger Circuits for Selective Trace Debugging
A separate configurable debug network monitors selected IC events and stores filtered trace data, cutting wasted resources and manual parsing.
- Driver Output Slew Rate Compensation Using Delay and Phase Detection
Direct time-domain feedback uses delay lines, comparators, and phase detection to hold driver slew rate within tight timing limits.
- Configurable Driver Circuit With Current Mirror Output Scaling
Digitally switching between current and voltage output, this driver circuit uses current mirrors to scale output accurately without shunt sensing losses.
- Programmable I/O Buffers for Low-Power Reconfigurable Thresholds
Configurable I/O buffers set direction, logic thresholds, drive strength, and resistors while limiting power and die area growth.
- IC Output Terminal Backup Using Level Shifters and Memory Cells
Memory cells in voltage level shifters preserve IC output states during low-power idle mode, cutting power use without losing logic levels.
- PLD Configuration Port Data Transfer for Low-Bandwidth I/O
Repurposing a PLD configuration port moves low-bandwidth communication data through I/O blocks, freeing logic and interconnect resources.
- Semiconductor Signal Timing Adjustment for Variable Voltage and Clock Modes
Voltage and clock detection select delay parameters to preserve signal margin and prevent memory malfunctions under direct external power.
- Programmable I/O Gate Voltage Configuration for PCB Compatibility
A control circuit sets programmable I/O gate voltage levels so one PCB can interface with logic chips across changing I/O standards.
- Multiplexed Voltage Level Translation in Buffer Circuits
A shared level translator lets mode-dependent control signals drive a buffer across voltage domains while cutting translator count and chip area.
- Hybrid Hall Effect Magnetoelectronic Gate for Nonvolatile Logic
Integrating CMOS buffers with hybrid hall effect devices resolves fanout limitations in nonvolatile logic circuits.
- Configurable Diode Package for Digital Connection Module
A configurable diode package merges input resistor and pull up or pull down mode selection into a single circuit location.
- Data Flow Processor Power Control via Circular Buffer Sleep States
Circular buffers manage sleep states in data flow processors to conserve power.
- Bias Voltage Generator for Stable Data Output Clock Signal
A bias voltage generator adjusts potential difference to buffer external clock signals for semiconductor integrated circuits.
- Configurable Mixed Signal Interface Blocks for IC Pin Flexibility
Segmented mixed signal interface blocks eliminate resource sharing conflicts, enabling independent operation of diverse signal functions.
- Flexible Interface Block for Semiconductor Die Coupling
Programmable logic in a flexible interface block supports diverse protocols while reducing interfacing complexity between multiple semiconductor dies.
- Out-of-band differential pin driver with multi-level signaling
Segmented current sources in a differential pin driver enable multi-level signaling to overcome the two-level limitation of conventional designs.
- Programmable Array Signal Routing for 3D IC Die Stacks
Dynamic signal routing via programmable arrays bypasses failed dies in 3D stacks, improving yield and reliability.