Multiplexed Voltage Level Translation in Buffer Circuits
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Solution Overview
Problem
Conventional bidirectional buffer circuits require multiple voltage level translator circuits, consuming significant chip area due to the need for voltage level translation of control signals across different voltage domains in portable devices, which increases the size of integrated circuits.
Innovation Solution
The implementation of a multiplexing technique that allows two or more control signals to share a single voltage level translator circuit, reducing the number of translator circuits needed and minimizing chip area by exploiting modes of operation where certain signals have no effect on other circuit portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple voltage level translator circuits are used for each control signal, then voltage level translation is achieved, but chip area increases significantly
Solution Approach 1:
Multiple control signals that operate in different modes are merged to share a single voltage level translator circuit. The buffer circuit can operate in different modes (input mode, output mode, high-impedance mode) and only the relevant control signals are active in each mode, allowing consolidation of translator resources.
Solution Approach 2:
A single voltage level translator circuit is designed to handle multiple control signals universally. The translator circuit can be selectively enabled for different signals based on the operational mode, making one circuit perform the function of multiple dedicated translators.
2Reliability
If each control signal has its own voltage level translator circuit, then signal translation accuracy is maintained, but device complexity increases
Solution Approach 1:
The buffer circuit employs dynamic mode switching between input mode, output mode, and high-impedance mode. Control signals are selectively activated based on the current mode, allowing a single translator circuit to dynamically serve different signals at different times rather than requiring static dedicated translators for each signal.
Solution Approach 2:
Control signals are activated in periodic or sequential manner corresponding to different operational modes. During input mode, input control signals are active; during output mode, output control signals are active. This periodic activation pattern enables time-division sharing of the translator circuit.
Data Source
AI summary
A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.