Transparent-Latch Dynamic Register for Shorter Setup Times
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Solution Overview
Problem
Dynamic logic circuits often exhibit long setup and hold times, necessitating improved efficiency in fast dynamic register circuits without the overhead of pulsed clock circuits.
Innovation Solution
A fast dynamic register circuit is designed with a data block, precharge circuit, transparent latch, and output logic gate, featuring transistors and a keeper circuit to minimize setup times and implement a scan mode for efficient data registration, utilizing a scan enable block and select gate to manage precharge and discharge nodes based on clock states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dynamic logic circuits use conventional latch designs, then reliability is maintained, but setup and hold times become excessively long
Solution Approach 1:
The precharge circuit precharges the dynamic node before the clock edge arrives, ensuring the node is ready for immediate evaluation. This preliminary action eliminates the need for long setup times while maintaining reliable operation through proper voltage levels.
Solution Approach 2:
The circuit uses dynamic evaluation where the latch transitions from a transparent state during the precharge phase to a latched state during evaluation. This dynamic behavior allows the circuit to adapt its functionality based on the clock phase, achieving both fast setup times and reliable operation.
2Speed
If pulsed clock circuits are used to reduce setup times, then speed is improved, but device complexity increases
Solution Approach 1:
The transparent latch serves multiple functions: it acts as a buffer during the precharge phase and as a storage element during the evaluation phase. This multi-functionality eliminates the need for separate pulsed clock circuits while maintaining high-speed operation.
Solution Approach 2:
The latch automatically transitions between transparent and latched states based on the clock signal phase, without requiring external control logic. The circuit self-regulates its operation mode, reducing the need for additional control circuitry and simplifying the overall design.
Data Source
AI summary
A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency.