Reconfigurable Logic Tile for Dynamic ASIC Adaptation

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Solution Overview

Problem

ASICs are inflexible and costly to modify once built, requiring a complete rebuild for changes, while reconfigurable logic devices offer flexibility but are inefficient in area, speed, and cost compared to ASICs.

Innovation Solution

An ASIC with a digital signal processing core and a configurable logic block featuring interconnected logic modules with dynamic reconfiguration capabilities, allowing logic functions and interconnections to be reconfigured by a controller during operation, enabling time-sliced changes in clock-cycle connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an ASIC is built with fixed logic functions, then area efficiency and performance are improved, but adaptability deteriorates

Engineering Contradiction:
ImproveperformanceVSAvoidadaptability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic reconfiguration of logic functions within the ASIC by dividing the logic into multiple reconfigurable modules that can be dynamically programmed and reprogrammed during operation, allowing the system to adapt its logic functions while maintaining area efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent creates universal logic modules that can perform multiple different logic functions through reconfiguration, allowing a single ASIC to serve multiple purposes and adapt to different computational requirements without requiring separate dedicated hardware for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If reconfigurable logic devices are used to improve adaptability, then adaptability is improved, but area efficiency and speed deteriorate

Engineering Contradiction:
ImproveflexibilityVSAvoidarea efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the logic functionality into discrete reconfigurable modules that can be independently controlled and configured, allowing efficient utilization of silicon area while maintaining reconfigurability, as each module can be optimized for its specific function at any given time

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If reconfigurable logic devices are used to improve adaptability, then adaptability is improved, but manufacturing cost deteriorates

Engineering Contradiction:
ImproveflexibilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent implements dynamic reconfiguration capabilities that allow a single ASIC design to serve multiple applications, eliminating the need to manufacture separate ASICs for different functions, thereby reducing overall manufacturing costs while maintaining high adaptability

Inventive Principle:
Principle #15Dynamics

4Adaptability or versatility

If ASIC is rebuilt to modify logic functions, then adaptability is improved, but time consumption and cost deteriorate

Engineering Contradiction:
ImprovemodifiabilityVSAvoidrebuild time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements dynamic reconfiguration capabilities that allow logic functions to be modified in real-time or between operations without requiring physical rebuilding of the ASIC, enabling rapid adaptation to new requirements while maintaining the area efficiency and performance of fixed ASIC technology

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20140285233A1Efficient reconfigurable logic tile
Publication Date: 2014.09.25 TEXAS INSTRUMENTS INC
  • US20140285233A1 patent drawing
  • US20140285233A1 patent drawing
  • US20140285233A1 patent drawing

AI summary

An application specific integrated circuit (ASIC) that includes a digital signal processing (DSP) core and a configurable logic block coupled to the DSP core. The configurable logic block including a plurality of interconnected logic modules to apply a pre-configured logic function to an input. Each of the plurality of logic modules including a controller and a plurality of logic components, the controller of each logic module dynamically reconfigures the connections between the controller's logic module and another logic module.